427 lines
12 KiB
C++
427 lines
12 KiB
C++
// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Pica {
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struct TexturingRegs {
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struct TextureConfig {
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enum TextureType : u32 {
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Texture2D = 0,
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TextureCube = 1,
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Shadow2D = 2,
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Projection2D = 3,
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ShadowCube = 4,
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Disabled = 5,
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};
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enum WrapMode : u32 {
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ClampToEdge = 0,
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ClampToBorder = 1,
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Repeat = 2,
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MirroredRepeat = 3,
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// Mode 4-7 produces some weird result and may be just invalid:
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ClampToEdge2 = 4, // Positive coord: clamp to edge; negative coord: repeat
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ClampToBorder2 = 5, // Positive coord: clamp to border; negative coord: repeat
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Repeat2 = 6, // Same as Repeat
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Repeat3 = 7, // Same as Repeat
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};
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enum TextureFilter : u32 {
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Nearest = 0,
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Linear = 1,
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};
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} border_color;
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union {
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BitField<0, 11, u32> height;
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BitField<16, 11, u32> width;
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};
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union {
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BitField<1, 1, TextureFilter> mag_filter;
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BitField<2, 1, TextureFilter> min_filter;
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BitField<8, 3, WrapMode> wrap_t;
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BitField<12, 3, WrapMode> wrap_s;
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/// @note Only valid for texture 0 according to 3DBrew.
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BitField<28, 3, TextureType> type;
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};
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 28, u32> address;
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PAddr GetPhysicalAddress() const {
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return address * 8;
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}
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// texture1 and texture2 store the texture format directly after the address
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// whereas texture0 inserts some additional flags inbetween.
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// Hence, we store the format separately so that all other parameters can be described
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// in a single structure.
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};
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enum class TextureFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB5A1 = 2,
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RGB565 = 3,
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RGBA4 = 4,
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IA8 = 5,
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RG8 = 6, ///< @note Also called HILO8 in 3DBrew.
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I8 = 7,
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A8 = 8,
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IA4 = 9,
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I4 = 10,
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A4 = 11,
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ETC1 = 12, // compressed
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ETC1A4 = 13, // compressed
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};
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static unsigned NibblesPerPixel(TextureFormat format) {
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switch (format) {
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case TextureFormat::RGBA8:
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return 8;
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case TextureFormat::RGB8:
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return 6;
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case TextureFormat::RGB5A1:
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case TextureFormat::RGB565:
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case TextureFormat::RGBA4:
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case TextureFormat::IA8:
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case TextureFormat::RG8:
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return 4;
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case TextureFormat::I4:
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case TextureFormat::A4:
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return 1;
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case TextureFormat::I8:
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case TextureFormat::A8:
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case TextureFormat::IA4:
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default: // placeholder for yet unknown formats
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UNIMPLEMENTED();
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return 0;
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}
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}
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union {
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BitField<0, 1, u32> texture0_enable;
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BitField<1, 1, u32> texture1_enable;
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BitField<2, 1, u32> texture2_enable;
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BitField<8, 2, u32> texture3_coordinates;
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BitField<10, 1, u32> texture3_enable;
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BitField<13, 1, u32> texture2_use_coord1;
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BitField<16, 1, u32> clear_texture_cache; // TODO: unimplemented
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} main_config;
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TextureConfig texture0;
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INSERT_PADDING_WORDS(0x8);
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BitField<0, 4, TextureFormat> texture0_format;
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BitField<0, 1, u32> fragment_lighting_enable;
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INSERT_PADDING_WORDS(0x1);
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TextureConfig texture1;
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BitField<0, 4, TextureFormat> texture1_format;
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INSERT_PADDING_WORDS(0x2);
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TextureConfig texture2;
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BitField<0, 4, TextureFormat> texture2_format;
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INSERT_PADDING_WORDS(0x9);
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struct FullTextureConfig {
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const bool enabled;
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const TextureConfig config;
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const TextureFormat format;
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};
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const std::array<FullTextureConfig, 3> GetTextures() const {
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return {{
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{main_config.texture0_enable.ToBool(), texture0, texture0_format},
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{main_config.texture1_enable.ToBool(), texture1, texture1_format},
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{main_config.texture2_enable.ToBool(), texture2, texture2_format},
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}};
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}
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// 0xa8-0xad: ProcTex Config
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enum class ProcTexClamp : u32 {
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ToZero = 0,
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ToEdge = 1,
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SymmetricalRepeat = 2,
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MirroredRepeat = 3,
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Pulse = 4,
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};
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enum class ProcTexCombiner : u32 {
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U = 0, // u
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U2 = 1, // u * u
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V = 2, // v
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V2 = 3, // v * v
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Add = 4, // (u + v) / 2
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Add2 = 5, // (u * u + v * v) / 2
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SqrtAdd2 = 6, // sqrt(u * u + v * v)
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Min = 7, // min(u, v)
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Max = 8, // max(u, v)
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RMax = 9, // Average of Max and SqrtAdd2
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};
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enum class ProcTexShift : u32 {
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None = 0,
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Odd = 1,
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Even = 2,
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};
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union {
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BitField<0, 3, ProcTexClamp> u_clamp;
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BitField<3, 3, ProcTexClamp> v_clamp;
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BitField<6, 4, ProcTexCombiner> color_combiner;
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BitField<10, 4, ProcTexCombiner> alpha_combiner;
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BitField<14, 1, u32> separate_alpha;
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BitField<15, 1, u32> noise_enable;
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BitField<16, 2, ProcTexShift> u_shift;
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BitField<18, 2, ProcTexShift> v_shift;
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BitField<20, 8, u32> bias_low; // float16 TODO: unimplemented
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} proctex;
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union ProcTexNoiseConfig {
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BitField<0, 16, s32> amplitude; // fixed1.3.12
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BitField<16, 16, u32> phase; // float16
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};
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ProcTexNoiseConfig proctex_noise_u;
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ProcTexNoiseConfig proctex_noise_v;
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union {
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BitField<0, 16, u32> u; // float16
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BitField<16, 16, u32> v; // float16
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} proctex_noise_frequency;
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enum class ProcTexFilter : u32 {
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Nearest = 0,
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Linear = 1,
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NearestMipmapNearest = 2,
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LinearMipmapNearest = 3,
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NearestMipmapLinear = 4,
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LinearMipmapLinear = 5,
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};
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union {
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BitField<0, 3, ProcTexFilter> filter;
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BitField<11, 8, u32> width;
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BitField<19, 8, u32> bias_high; // TODO: unimplemented
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} proctex_lut;
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BitField<0, 8, u32> proctex_lut_offset;
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INSERT_PADDING_WORDS(0x1);
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// 0xaf-0xb7: ProcTex LUT
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enum class ProcTexLutTable : u32 {
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Noise = 0,
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ColorMap = 2,
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AlphaMap = 3,
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Color = 4,
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ColorDiff = 5,
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};
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union {
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BitField<0, 8, u32> index;
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BitField<8, 4, ProcTexLutTable> ref_table;
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} proctex_lut_config;
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u32 proctex_lut_data[8];
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INSERT_PADDING_WORDS(0x8);
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// 0xc0-0xff: Texture Combiner (akin to glTexEnv)
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struct TevStageConfig {
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enum class Source : u32 {
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PrimaryColor = 0x0,
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PrimaryFragmentColor = 0x1,
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SecondaryFragmentColor = 0x2,
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Texture0 = 0x3,
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Texture1 = 0x4,
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Texture2 = 0x5,
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Texture3 = 0x6,
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PreviousBuffer = 0xd,
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Constant = 0xe,
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Previous = 0xf,
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};
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enum class ColorModifier : u32 {
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SourceColor = 0x0,
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OneMinusSourceColor = 0x1,
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SourceAlpha = 0x2,
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OneMinusSourceAlpha = 0x3,
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SourceRed = 0x4,
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OneMinusSourceRed = 0x5,
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SourceGreen = 0x8,
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OneMinusSourceGreen = 0x9,
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SourceBlue = 0xc,
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OneMinusSourceBlue = 0xd,
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};
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enum class AlphaModifier : u32 {
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SourceAlpha = 0x0,
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OneMinusSourceAlpha = 0x1,
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SourceRed = 0x2,
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OneMinusSourceRed = 0x3,
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SourceGreen = 0x4,
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OneMinusSourceGreen = 0x5,
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SourceBlue = 0x6,
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OneMinusSourceBlue = 0x7,
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};
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enum class Operation : u32 {
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Replace = 0,
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Modulate = 1,
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Add = 2,
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AddSigned = 3,
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Lerp = 4,
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Subtract = 5,
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Dot3_RGB = 6,
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Dot3_RGBA = 7,
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MultiplyThenAdd = 8,
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AddThenMultiply = 9,
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};
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union {
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u32 sources_raw;
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BitField<0, 4, Source> color_source1;
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BitField<4, 4, Source> color_source2;
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BitField<8, 4, Source> color_source3;
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BitField<16, 4, Source> alpha_source1;
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BitField<20, 4, Source> alpha_source2;
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BitField<24, 4, Source> alpha_source3;
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};
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union {
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u32 modifiers_raw;
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BitField<0, 4, ColorModifier> color_modifier1;
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BitField<4, 4, ColorModifier> color_modifier2;
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BitField<8, 4, ColorModifier> color_modifier3;
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BitField<12, 3, AlphaModifier> alpha_modifier1;
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BitField<16, 3, AlphaModifier> alpha_modifier2;
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BitField<20, 3, AlphaModifier> alpha_modifier3;
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};
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union {
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u32 ops_raw;
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BitField<0, 4, Operation> color_op;
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BitField<16, 4, Operation> alpha_op;
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};
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union {
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u32 const_color;
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BitField<0, 8, u32> const_r;
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BitField<8, 8, u32> const_g;
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BitField<16, 8, u32> const_b;
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BitField<24, 8, u32> const_a;
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};
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union {
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u32 scales_raw;
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BitField<0, 2, u32> color_scale;
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BitField<16, 2, u32> alpha_scale;
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};
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inline unsigned GetColorMultiplier() const {
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return (color_scale < 3) ? (1 << color_scale) : 1;
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}
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inline unsigned GetAlphaMultiplier() const {
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return (alpha_scale < 3) ? (1 << alpha_scale) : 1;
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}
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};
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TevStageConfig tev_stage0;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage1;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage2;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x3);
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enum class FogMode : u32 {
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None = 0,
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Fog = 5,
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Gas = 7,
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};
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union {
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BitField<0, 3, FogMode> fog_mode;
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BitField<16, 1, u32> fog_flip;
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField<8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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};
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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} fog_color;
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INSERT_PADDING_WORDS(0x4);
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BitField<0, 16, u32> fog_lut_offset;
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INSERT_PADDING_WORDS(0x1);
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u32 fog_lut_data[8];
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} tev_combiner_buffer_color;
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INSERT_PADDING_WORDS(0x2);
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const std::array<TevStageConfig, 6> GetTevStages() const {
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return {{tev_stage0, tev_stage1, tev_stage2, tev_stage3, tev_stage4, tev_stage5}};
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};
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};
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static_assert(sizeof(TexturingRegs) == 0x80 * sizeof(u32),
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"TexturingRegs struct has incorrect size");
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} // namespace Pica
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