2016-07-04 14:37:50 +01:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/assert.h"
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#include "frontend/arm_types.h"
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2016-07-14 13:28:20 +01:00
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#include "frontend/decoder/arm.h"
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2016-08-06 17:21:29 +01:00
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#include "frontend/decoder/vfp2.h"
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2016-07-04 14:37:50 +01:00
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#include "frontend/ir/ir.h"
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2016-07-18 09:25:33 +01:00
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#include "frontend/translate/translate.h"
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2016-08-01 20:20:22 +01:00
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#include "frontend/translate/translate_arm/translate_arm.h"
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2016-07-04 14:37:50 +01:00
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namespace Dynarmic {
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namespace Arm {
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IR::Block TranslateArm(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32) {
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2016-07-14 13:28:20 +01:00
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ArmTranslatorVisitor visitor{descriptor};
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bool should_continue = true;
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2016-07-14 14:04:43 +01:00
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while (should_continue && visitor.cond_state == ConditionalState::None) {
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2016-08-01 20:03:13 +01:00
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const u32 arm_pc = visitor.ir.current_location.PC();
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2016-07-14 13:28:20 +01:00
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const u32 arm_instruction = (*memory_read_32)(arm_pc);
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2016-08-06 17:21:29 +01:00
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if (auto vfp_decoder = DecodeVFP2<ArmTranslatorVisitor>(arm_instruction)) {
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should_continue = vfp_decoder->call(visitor, arm_instruction);
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} else if (auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction)) {
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2016-07-14 13:28:20 +01:00
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should_continue = decoder->call(visitor, arm_instruction);
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} else {
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should_continue = visitor.arm_UDF();
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}
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2016-07-14 14:04:43 +01:00
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if (visitor.cond_state == ConditionalState::Break) {
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break;
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}
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2016-08-01 20:03:13 +01:00
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visitor.ir.current_location = visitor.ir.current_location.AdvancePC(4);
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2016-07-14 13:28:20 +01:00
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visitor.ir.block.cycle_count++;
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}
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2016-07-14 14:04:43 +01:00
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if (visitor.cond_state == ConditionalState::Translating) {
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if (should_continue) {
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visitor.ir.SetTerm(IR::Term::LinkBlock{visitor.ir.current_location});
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}
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visitor.ir.block.cond_failed = { visitor.ir.current_location };
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}
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2016-07-22 23:55:00 +01:00
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return std::move(visitor.ir.block);
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2016-07-04 14:37:50 +01:00
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}
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2016-08-01 20:20:22 +01:00
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bool ArmTranslatorVisitor::ConditionPassed(Cond cond) {
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ASSERT_MSG(cond_state != ConditionalState::Translating,
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"In the current impl, ConditionPassed should never be called again once a non-AL cond is hit. "
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"(i.e.: one and only one conditional instruction per block)");
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ASSERT_MSG(cond_state != ConditionalState::Break,
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"This should never happen. We requested a break but that wasn't honored.");
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if (cond == Cond::AL) {
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// Everything is fine with the world
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return true;
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}
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2016-08-05 04:14:15 +01:00
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if (cond == Cond::NV) {
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// NV conditional is obsolete, but still seems to be used in some places!
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return false;
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}
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2016-08-01 20:20:22 +01:00
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// non-AL cond
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2016-08-06 22:23:01 +01:00
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if (!ir.block.instructions.IsEmpty()) {
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2016-08-01 20:20:22 +01:00
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// We've already emitted instructions. Quit for now, we'll make a new block here later.
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cond_state = ConditionalState::Break;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location});
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return false;
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}
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// We've not emitted instructions yet.
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// We'll emit one instruction, and set the block-entry conditional appropriately.
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cond_state = ConditionalState::Translating;
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ir.block.cond = cond;
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return true;
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}
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bool ArmTranslatorVisitor::InterpretThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(ir.current_location));
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return false;
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}
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bool ArmTranslatorVisitor::UnpredictableInstruction() {
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ASSERT_MSG(false, "UNPREDICTABLE");
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return false;
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}
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bool ArmTranslatorVisitor::LinkToNextInstruction() {
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auto next_location = ir.current_location.AdvancePC(4);
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ir.SetTerm(IR::Term::LinkBlock{next_location});
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return false;
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}
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
2016-08-03 00:44:35 +01:00
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IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in) {
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IREmitter::ResultAndCarry result_and_carry;
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switch (type)
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{
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case ShiftType::LSL:
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result_and_carry = ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in);
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break;
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case ShiftType::LSR:
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imm5 = imm5 ? imm5 : 32;
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result_and_carry = ir.LogicalShiftRight(value, ir.Imm8(imm5), carry_in);
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break;
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case ShiftType::ASR:
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imm5 = imm5 ? imm5 : 32;
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result_and_carry = ir.ArithmeticShiftRight(value, ir.Imm8(imm5), carry_in);
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break;
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case ShiftType::ROR:
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if (imm5)
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result_and_carry = ir.RotateRight(value, ir.Imm8(imm5), carry_in);
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else
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result_and_carry = ir.RotateRightExtended(value, carry_in);
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break;
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}
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return result_and_carry;
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}
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IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in) {
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IREmitter::ResultAndCarry result_and_carry;
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switch (type)
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{
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case ShiftType::LSL:
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result_and_carry = ir.LogicalShiftLeft(value, amount, carry_in);
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break;
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case ShiftType::LSR:
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result_and_carry = ir.LogicalShiftRight(value, amount, carry_in);
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break;
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case ShiftType::ASR:
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result_and_carry = ir.ArithmeticShiftRight(value, amount, carry_in);
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break;
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case ShiftType::ROR:
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result_and_carry = ir.RotateRight(value, amount, carry_in);
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break;
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}
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return result_and_carry;
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}
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2016-07-04 14:37:50 +01:00
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} // namespace Arm
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} // namespace Dynarmic
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