2016-07-04 10:22:11 +01:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <memory>
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2017-12-05 21:34:40 +00:00
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#include <boost/icl/interval_set.hpp>
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2016-08-25 23:41:31 +01:00
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#include <fmt/format.h>
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2016-08-05 01:50:31 +01:00
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#ifdef DYNARMIC_USE_LLVM
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#include <llvm-c/Disassembler.h>
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#include <llvm-c/Target.h>
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#endif
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2016-08-07 18:08:48 +01:00
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#include "backend_x64/block_of_code.h"
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2016-07-04 10:22:11 +01:00
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#include "backend_x64/emit_x64.h"
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#include "backend_x64/jitstate.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/scope_exit.h"
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2017-12-03 18:25:40 +00:00
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#include "dynarmic/context.h"
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2016-08-25 18:22:08 +01:00
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#include "dynarmic/dynarmic.h"
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2016-09-03 21:48:03 +01:00
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#include "frontend/ir/basic_block.h"
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2016-09-05 11:54:09 +01:00
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#include "frontend/ir/location_descriptor.h"
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2016-07-14 14:39:43 +01:00
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#include "frontend/translate/translate.h"
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2016-07-21 21:48:45 +01:00
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#include "ir_opt/passes.h"
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2016-07-04 10:22:11 +01:00
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namespace Dynarmic {
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using namespace BackendX64;
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struct Jit::Impl {
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2016-08-13 00:10:23 +01:00
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Impl(Jit* jit, UserCallbacks callbacks)
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2017-04-07 10:52:44 +01:00
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: block_of_code(callbacks, &GetCurrentBlock, this)
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2016-08-31 21:57:33 +01:00
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, jit_state()
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2016-08-13 00:10:23 +01:00
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, emitter(&block_of_code, callbacks, jit)
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, callbacks(callbacks)
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2017-02-16 18:18:29 +00:00
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, jit_interface(jit)
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2016-08-13 00:10:23 +01:00
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{}
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BlockOfCode block_of_code;
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JitState jit_state;
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2016-07-04 10:22:11 +01:00
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EmitX64 emitter;
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2016-07-04 14:37:50 +01:00
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const UserCallbacks callbacks;
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2016-07-04 10:22:11 +01:00
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2017-02-16 18:18:29 +00:00
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// Requests made during execution to invalidate the cache are queued up here.
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2017-12-03 18:25:40 +00:00
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size_t invalid_cache_generation = 0;
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2017-12-05 21:34:40 +00:00
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boost::icl::interval_set<u32> invalid_cache_ranges;
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2017-09-11 00:09:52 +01:00
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bool invalidate_entire_cache = false;
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2016-09-02 10:58:37 +01:00
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2017-12-03 02:42:22 +00:00
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void Execute(size_t cycle_count) {
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block_of_code.RunCode(&jit_state, cycle_count);
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2016-07-04 10:22:11 +01:00
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}
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2016-08-05 01:50:31 +01:00
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2016-09-05 11:54:09 +01:00
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std::string Disassemble(const IR::LocationDescriptor& descriptor) {
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2016-08-05 01:50:31 +01:00
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auto block = GetBasicBlock(descriptor);
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2017-02-16 18:18:29 +00:00
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std::string result = fmt::format("address: {}\nsize: {} bytes\n", block.entrypoint, block.size);
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2016-08-05 01:50:31 +01:00
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#ifdef DYNARMIC_USE_LLVM
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LLVMInitializeX86TargetInfo();
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LLVMInitializeX86TargetMC();
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LLVMInitializeX86Disassembler();
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LLVMDisasmContextRef llvm_ctx = LLVMCreateDisasm("x86_64", nullptr, 0, nullptr, nullptr);
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LLVMSetDisasmOptions(llvm_ctx, LLVMDisassembler_Option_AsmPrinterVariant);
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2017-02-16 18:18:29 +00:00
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const u8* pos = static_cast<const u8*>(block.entrypoint);
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2017-03-06 23:29:36 +00:00
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const u8* end = pos + block.size;
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size_t remaining = block.size;
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while (pos < end) {
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2016-08-05 01:50:31 +01:00
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char buffer[80];
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size_t inst_size = LLVMDisasmInstruction(llvm_ctx, const_cast<u8*>(pos), remaining, (u64)pos, buffer, sizeof(buffer));
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2016-08-19 01:53:24 +01:00
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ASSERT(inst_size);
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2017-03-06 23:29:36 +00:00
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for (const u8* i = pos; i < pos + inst_size; i++)
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2016-08-25 23:41:31 +01:00
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result += fmt::format("{:02x} ", *i);
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2016-08-05 01:50:31 +01:00
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for (size_t i = inst_size; i < 10; i++)
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2016-08-25 23:41:31 +01:00
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result += " ";
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result += buffer;
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result += '\n';
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2016-08-05 01:50:31 +01:00
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pos += inst_size;
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remaining -= inst_size;
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}
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LLVMDisasmDispose(llvm_ctx);
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#else
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result.append("(recompile with DYNARMIC_USE_LLVM=ON to disassemble the generated x86_64 code)\n");
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#endif
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return result;
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}
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2017-02-16 18:18:29 +00:00
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void PerformCacheInvalidation() {
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2017-09-11 00:09:52 +01:00
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if (invalidate_entire_cache) {
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jit_state.ResetRSB();
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block_of_code.ClearCache();
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emitter.ClearCache();
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invalid_cache_ranges.clear();
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invalidate_entire_cache = false;
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2017-12-03 18:25:40 +00:00
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invalid_cache_generation++;
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2017-09-11 00:09:52 +01:00
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return;
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}
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2017-02-16 18:18:29 +00:00
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if (invalid_cache_ranges.empty()) {
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return;
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}
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2016-09-02 10:58:37 +01:00
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jit_state.ResetRSB();
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2017-12-05 21:34:40 +00:00
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emitter.InvalidateCacheRanges(invalid_cache_ranges);
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invalid_cache_ranges.clear();
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2017-12-03 18:25:40 +00:00
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invalid_cache_generation++;
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2017-02-16 18:18:29 +00:00
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}
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2017-09-11 00:09:52 +01:00
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void RequestCacheInvalidation() {
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2017-02-16 18:18:29 +00:00
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if (jit_interface->is_executing) {
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jit_state.halt_requested = true;
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return;
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}
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PerformCacheInvalidation();
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2016-09-02 10:58:37 +01:00
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}
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2016-07-04 10:22:11 +01:00
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private:
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2017-02-16 18:18:29 +00:00
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Jit* jit_interface;
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2017-04-07 10:52:44 +01:00
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static CodePtr GetCurrentBlock(void *this_voidptr) {
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Jit::Impl& this_ = *reinterpret_cast<Jit::Impl*>(this_voidptr);
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JitState& jit_state = this_.jit_state;
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u32 pc = jit_state.Reg[15];
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2017-12-02 13:55:04 +00:00
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Arm::PSR cpsr{jit_state.Cpsr()};
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2017-04-07 10:52:44 +01:00
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Arm::FPSCR fpscr{jit_state.FPSCR_mode};
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IR::LocationDescriptor descriptor{pc, cpsr, fpscr};
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return this_.GetBasicBlock(descriptor).entrypoint;
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}
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2016-09-05 11:54:09 +01:00
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EmitX64::BlockDescriptor GetBasicBlock(IR::LocationDescriptor descriptor) {
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2016-08-05 01:50:31 +01:00
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auto block = emitter.GetBasicBlock(descriptor);
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if (block)
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2016-08-12 18:17:31 +01:00
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return *block;
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2016-07-04 10:22:11 +01:00
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2017-12-03 14:32:01 +00:00
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constexpr size_t MINIMUM_REMAINING_CODESIZE = 1 * 1024 * 1024;
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if (block_of_code.SpaceRemaining() < MINIMUM_REMAINING_CODESIZE) {
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invalidate_entire_cache = true;
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PerformCacheInvalidation();
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}
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2017-01-30 21:42:17 +00:00
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IR::Block ir_block = Arm::Translate(descriptor, callbacks.memory.ReadCode);
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2016-07-21 21:48:45 +01:00
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Optimization::GetSetElimination(ir_block);
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2017-02-19 11:05:16 +00:00
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Optimization::DeadCodeElimination(ir_block);
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2017-01-30 21:43:40 +00:00
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Optimization::ConstantPropagation(ir_block, callbacks.memory);
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2016-07-21 21:48:45 +01:00
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Optimization::DeadCodeElimination(ir_block);
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Optimization::VerificationPass(ir_block);
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2016-08-26 19:14:25 +01:00
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return emitter.Emit(ir_block);
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2016-07-04 10:22:11 +01:00
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}
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};
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2016-07-12 14:31:43 +01:00
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Jit::Jit(UserCallbacks callbacks) : impl(std::make_unique<Impl>(this, callbacks)) {}
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2016-07-04 10:22:11 +01:00
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Jit::~Jit() {}
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2017-12-03 02:42:22 +00:00
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void Jit::Run(size_t cycle_count) {
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2016-07-04 10:22:11 +01:00
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ASSERT(!is_executing);
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is_executing = true;
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SCOPE_EXIT({ this->is_executing = false; });
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2016-08-15 15:02:08 +01:00
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impl->jit_state.halt_requested = false;
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2016-07-04 10:22:11 +01:00
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2017-12-03 02:42:22 +00:00
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impl->Execute(cycle_count);
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2016-07-04 10:22:11 +01:00
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2017-02-16 18:18:29 +00:00
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impl->PerformCacheInvalidation();
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2016-07-04 10:22:11 +01:00
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}
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2016-09-01 09:47:09 +01:00
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void Jit::ClearCache() {
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2017-09-11 00:09:52 +01:00
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impl->invalidate_entire_cache = true;
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impl->RequestCacheInvalidation();
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2017-02-16 18:18:29 +00:00
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}
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2016-09-02 10:58:37 +01:00
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2017-02-16 18:18:29 +00:00
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void Jit::InvalidateCacheRange(std::uint32_t start_address, std::size_t length) {
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2017-12-07 20:26:46 +00:00
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impl->invalid_cache_ranges.add(boost::icl::discrete_interval<u32>::closed(start_address, static_cast<u32>(start_address + length - 1)));
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2017-09-11 00:09:52 +01:00
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impl->RequestCacheInvalidation();
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2016-07-04 10:22:11 +01:00
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}
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2016-08-09 22:45:54 +01:00
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void Jit::Reset() {
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ASSERT(!is_executing);
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2016-08-31 21:57:33 +01:00
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impl->jit_state = {};
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2016-08-09 22:45:54 +01:00
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}
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2016-07-04 10:22:11 +01:00
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void Jit::HaltExecution() {
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2016-08-15 15:02:08 +01:00
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impl->jit_state.halt_requested = true;
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2016-07-04 10:22:11 +01:00
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}
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std::array<u32, 16>& Jit::Regs() {
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return impl->jit_state.Reg;
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}
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2016-08-25 01:01:42 +01:00
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const std::array<u32, 16>& Jit::Regs() const {
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2016-07-04 10:22:11 +01:00
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return impl->jit_state.Reg;
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}
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2016-08-05 18:54:19 +01:00
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std::array<u32, 64>& Jit::ExtRegs() {
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return impl->jit_state.ExtReg;
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}
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2016-08-25 01:01:42 +01:00
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const std::array<u32, 64>& Jit::ExtRegs() const {
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2016-08-05 18:54:19 +01:00
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return impl->jit_state.ExtReg;
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}
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2017-12-02 13:55:04 +00:00
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u32 Jit::Cpsr() const {
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return impl->jit_state.Cpsr();
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2016-07-04 10:22:11 +01:00
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}
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2016-08-05 18:54:19 +01:00
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2017-12-02 13:55:04 +00:00
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void Jit::SetCpsr(u32 value) {
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return impl->jit_state.SetCpsr(value);
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2016-07-04 10:22:11 +01:00
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}
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2016-08-05 18:54:19 +01:00
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u32 Jit::Fpscr() const {
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return impl->jit_state.Fpscr();
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}
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2017-12-02 13:55:04 +00:00
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void Jit::SetFpscr(u32 value) {
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2016-08-05 18:54:19 +01:00
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return impl->jit_state.SetFpscr(value);
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}
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2017-12-03 18:25:40 +00:00
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Context Jit::SaveContext() const {
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Context ctx;
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SaveContext(ctx);
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return ctx;
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}
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struct Context::Impl {
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JitState jit_state;
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size_t invalid_cache_generation;
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};
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Context::Context() : impl(std::make_unique<Context::Impl>()) { impl->jit_state.ResetRSB(); }
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Context::~Context() = default;
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Context::Context(const Context& ctx) : impl(std::make_unique<Context::Impl>(*ctx.impl)) {}
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Context::Context(Context&& ctx) : impl(std::move(ctx.impl)) {}
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Context& Context::operator=(const Context& ctx) {
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*impl = *ctx.impl;
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return *this;
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}
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Context& Context::operator=(Context&& ctx) {
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impl = std::move(ctx.impl);
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return *this;
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}
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std::array<std::uint32_t, 16>& Context::Regs() {
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return impl->jit_state.Reg;
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}
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const std::array<std::uint32_t, 16>& Context::Regs() const {
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return impl->jit_state.Reg;
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}
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std::array<std::uint32_t, 64>& Context::ExtRegs() {
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return impl->jit_state.ExtReg;
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}
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const std::array<std::uint32_t, 64>& Context::ExtRegs() const {
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return impl->jit_state.ExtReg;
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}
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/// View and modify CPSR.
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std::uint32_t Context::Cpsr() const {
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return impl->jit_state.Cpsr();
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}
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void Context::SetCpsr(std::uint32_t value) {
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impl->jit_state.SetCpsr(value);
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}
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/// View and modify FPSCR.
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std::uint32_t Context::Fpscr() const {
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return impl->jit_state.Fpscr();
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}
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void Context::SetFpscr(std::uint32_t value) {
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return impl->jit_state.SetFpscr(value);
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}
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void TransferJitState(JitState& dest, const JitState& src, bool reset_rsb) {
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dest.CPSR_ge = src.CPSR_ge;
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dest.CPSR_et = src.CPSR_et;
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dest.CPSR_q = src.CPSR_q;
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dest.CPSR_nzcv = src.CPSR_nzcv;
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dest.CPSR_jaifm = src.CPSR_jaifm;
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dest.Reg = src.Reg;
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dest.ExtReg = src.ExtReg;
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dest.guest_MXCSR = src.guest_MXCSR;
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dest.FPSCR_IDC = src.FPSCR_IDC;
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dest.FPSCR_UFC = src.FPSCR_UFC;
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dest.FPSCR_mode = src.FPSCR_mode;
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dest.FPSCR_nzcv = src.FPSCR_nzcv;
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if (reset_rsb) {
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dest.ResetRSB();
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} else {
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dest.rsb_ptr = src.rsb_ptr;
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dest.rsb_location_descriptors = src.rsb_location_descriptors;
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dest.rsb_codeptrs = src.rsb_codeptrs;
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}
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}
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void Jit::SaveContext(Context& ctx) const {
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TransferJitState(ctx.impl->jit_state, impl->jit_state, false);
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ctx.impl->invalid_cache_generation = impl->invalid_cache_generation;
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}
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void Jit::LoadContext(const Context& ctx) {
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bool reset_rsb = ctx.impl->invalid_cache_generation != impl->invalid_cache_generation;
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TransferJitState(impl->jit_state, ctx.impl->jit_state, reset_rsb);
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}
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2016-09-05 11:54:09 +01:00
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std::string Jit::Disassemble(const IR::LocationDescriptor& descriptor) {
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2016-08-05 01:50:31 +01:00
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return impl->Disassemble(descriptor);
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}
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2016-07-04 10:22:11 +01:00
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} // namespace Dynarmic
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