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dynarmic/src/frontend/ir/opcodes.inc

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First Commit
2016-07-01 14:01:06 +01:00
// opcode name, return type, arg1 type, arg2 type, arg3 type, ...
ir_opt: Remove redundant shift instructions
2017-02-18 21:46:36 +00:00
OPCODE(Void, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
OPCODE(Identity, T::Opaque, T::Opaque )
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +01:00
OPCODE(Breakpoint, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
// A32 Context getters/setters
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2018-01-05 20:30:41 +00:00
A32OPC(GetRegister, T::U32, T::A32Reg )
A32OPC(GetExtendedRegister32, T::F32, T::A32ExtReg )
A32OPC(GetExtendedRegister64, T::F64, T::A32ExtReg )
A32OPC(SetRegister, T::Void, T::A32Reg, T::U32 )
A32OPC(SetExtendedRegister32, T::Void, T::A32ExtReg, T::F32 )
A32OPC(SetExtendedRegister64, T::Void, T::A32ExtReg, T::F64 )
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(GetCpsr, T::U32, )
A32OPC(SetCpsr, T::Void, T::U32 )
A32OPC(SetCpsrNZCV, T::Void, T::U32 )
A32OPC(SetCpsrNZCVQ, T::Void, T::U32 )
A32OPC(GetNFlag, T::U1, )
A32OPC(SetNFlag, T::Void, T::U1 )
A32OPC(GetZFlag, T::U1, )
A32OPC(SetZFlag, T::Void, T::U1 )
A32OPC(GetCFlag, T::U1, )
A32OPC(SetCFlag, T::Void, T::U1 )
A32OPC(GetVFlag, T::U1, )
A32OPC(SetVFlag, T::Void, T::U1 )
A32OPC(OrQFlag, T::Void, T::U1 )
A32OPC(GetGEFlags, T::U32, )
A32OPC(SetGEFlags, T::Void, T::U32 )
A32OPC(SetGEFlagsCompressed, T::Void, T::U32 )
A32OPC(BXWritePC, T::Void, T::U32 )
A32OPC(CallSupervisor, T::Void, T::U32 )
A32OPC(GetFpscr, T::U32, )
A32OPC(SetFpscr, T::Void, T::U32, )
A32OPC(GetFpscrNZCV, T::U32, )
A32OPC(SetFpscrNZCV, T::Void, T::U32, )
First Commit
2016-07-01 14:01:06 +01:00
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
// Hints
OPCODE(PushRSB, T::Void, T::U64 )
First Commit
2016-07-01 14:01:06 +01:00
// Pseudo-operation, handled specially at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
2016-07-08 10:09:18 +01:00
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
IR: Implement new pseudo-operation GetGEFromOp
2016-12-04 20:52:06 +00:00
OPCODE(GetGEFromOp, T::U32, T::U32 )
First Commit
2016-07-01 14:01:06 +01:00
// Calculations
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(Pack2x32To1x64, T::U64, T::U32, T::U32 )
OPCODE(LeastSignificantWord, T::U32, T::U64 )
OPCODE(MostSignificantWord, T::U32, T::U64 )
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
2016-07-11 23:06:35 +01:00
OPCODE(LeastSignificantHalf, T::U16, T::U32 )
First Commit
2016-07-01 14:01:06 +01:00
OPCODE(LeastSignificantByte, T::U8, T::U32 )
OPCODE(MostSignificantBit, T::U1, T::U32 )
OPCODE(IsZero, T::U1, T::U32 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(IsZero64, T::U1, T::U64 )
First Commit
2016-07-01 14:01:06 +01:00
OPCODE(LogicalShiftLeft, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftRight, T::U32, T::U32, T::U8, T::U1 )
Add simplified LogicalShiftRight64 IR opcode
2016-08-07 14:23:33 +01:00
OPCODE(LogicalShiftRight64, T::U64, T::U64, T::U8 )
Reorganisation, Import Skyeye, This is a mess
2016-07-04 10:22:11 +01:00
OPCODE(ArithmeticShiftRight, T::U32, T::U32, T::U8, T::U1 )
Implemented thumb1_ROR_reg
2016-07-10 01:18:17 +01:00
OPCODE(RotateRight, T::U32, T::U32, T::U8, T::U1 )
Add IR opcode RotateRightExtended to rotate through the carry flag
2016-07-31 19:07:35 +01:00
OPCODE(RotateRightExtended, T::U32, T::U32, T::U1 )
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
2016-07-08 10:09:18 +01:00
OPCODE(AddWithCarry, T::U32, T::U32, T::U32, T::U1 )
Implement thumb1_SUB_reg
2016-07-08 11:49:30 +01:00
OPCODE(SubWithCarry, T::U32, T::U32, T::U32, T::U1 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(Add64, T::U64, T::U64, T::U64 )
Add Sub64 opcode
2016-08-06 06:09:47 +01:00
OPCODE(Sub64, T::U64, T::U64, T::U64 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(Mul, T::U32, T::U32, T::U32 )
OPCODE(Mul64, T::U64, T::U64, T::U64 )
Implement thumb1_AND_reg
2016-07-08 10:43:28 +01:00
OPCODE(And, T::U32, T::U32, T::U32 )
Implement thumb1_EOR_reg
2016-07-08 11:14:50 +01:00
OPCODE(Eor, T::U32, T::U32, T::U32 )
Implement thumb1_ORR_reg
2016-07-10 02:06:38 +01:00
OPCODE(Or, T::U32, T::U32, T::U32 )
Implement thumb1_BIC_reg
2016-07-10 03:44:45 +01:00
OPCODE(Not, T::U32, T::U32 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(SignExtendWordToLong, T::U64, T::U32 )
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
OPCODE(SignExtendHalfToWord, T::U32, T::U16 )
OPCODE(SignExtendByteToWord, T::U32, T::U8 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(ZeroExtendWordToLong, T::U64, T::U32 )
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
OPCODE(ZeroExtendHalfToWord, T::U32, T::U16 )
OPCODE(ZeroExtendByteToWord, T::U32, T::U8 )
OPCODE(ByteReverseWord, T::U32, T::U32 )
OPCODE(ByteReverseHalf, T::U16, T::U16 )
Implement memory endianness. Implement Thumb SETEND instruction.
2016-07-20 15:34:17 +01:00
OPCODE(ByteReverseDual, T::U64, T::U64 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
OPCODE(CountLeadingZeros, T::U32, T::U32 )
// Saturated instructions
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub, T::U32, T::U32, T::U32 )
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 14:16:48 +00:00
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(SignedSaturation, T::U32, T::U32, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Packed instructions
Implement UADD8
2016-12-04 20:52:33 +00:00
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-18 16:25:41 +00:00
OPCODE(PackedAddS8, T::U32, T::U32, T::U32 )
Implement USUB8
2016-12-05 00:27:59 +00:00
OPCODE(PackedSubU8, T::U32, T::U32, T::U32 )
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-18 16:25:41 +00:00
OPCODE(PackedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS16, T::U32, T::U32, T::U32 )
parallel: Add and Subtract with Exchange improvements * Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction * Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions * Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
OPCODE(PackedAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddS16, T::U32, T::U32, T::U32 )
Implemented the ARM UHADD8 instruction. (#45) The x64 implementation uses the SSSE3 instruction PSHUFB. A non-SSE fallback is provided in case the CPU doesn't support it.
2016-11-25 20:32:22 +00:00
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
Implement SHADD8 and SHADD16 (#47)
2016-11-26 18:12:29 +00:00
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
Implement UHSUB8 and UHSUB16 (#48)
2016-11-26 18:27:21 +00:00
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )
Implement SHSUB8 and SHSUB16 (#74) * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
OPCODE(PackedHalvingSubS8, T::U32, T::U32, T::U32 )
Implemented UHADD16
2016-11-26 11:28:20 +00:00
OPCODE(PackedHalvingAddU16, T::U32, T::U32, T::U32 )
Implement SHADD8 and SHADD16 (#47)
2016-11-26 18:12:29 +00:00
OPCODE(PackedHalvingAddS16, T::U32, T::U32, T::U32 )
Implement UHSUB8 and UHSUB16 (#48)
2016-11-26 18:27:21 +00:00
OPCODE(PackedHalvingSubU16, T::U32, T::U32, T::U32 )
Implement SHSUB8 and SHSUB16 (#74) * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
OPCODE(PackedHalvingSubS16, T::U32, T::U32, T::U32 )
parallel: Add and Subtract with Exchange improvements * Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction * Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions * Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
OPCODE(PackedHalvingAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32 )
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 18:26:14 +01:00
OPCODE(PackedSaturatedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS8, T::U32, T::U32, T::U32 )
TranslateArm: Implement UQSUB8.
2016-08-12 16:53:16 +01:00
OPCODE(PackedSaturatedSubU8, T::U32, T::U32, T::U32 )
TranslateArm: Implement QSUB8.
2016-08-12 18:18:38 +01:00
OPCODE(PackedSaturatedSubS8, T::U32, T::U32, T::U32 )
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 18:42:16 +01:00
OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
Implemented USAD8 and USADA8
2016-12-17 19:52:22 +00:00
OPCODE(PackedAbsDiffSumS8, T::U32, T::U32, T::U32 )
Implement IR instruction PackedSelect, reimplement SEL
2017-11-25 16:33:48 +00:00
OPCODE(PackedSelect, T::U32, T::U32, T::U32, T::U32 )
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point operations
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
OPCODE(TransferToFP32, T::F32, T::U32 )
OPCODE(TransferToFP64, T::F64, T::U64 )
OPCODE(TransferFromFP32, T::U32, T::F32 )
OPCODE(TransferFromFP64, T::U64, T::F64 )
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
OPCODE(FPAbs32, T::F32, T::F32 )
OPCODE(FPAbs64, T::F64, T::F64 )
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
OPCODE(FPAdd32, T::F32, T::F32, T::F32 )
OPCODE(FPAdd64, T::F64, T::F64, T::F64 )
Implement VCMP
2016-11-26 11:17:16 +00:00
OPCODE(FPCompare32, T::Void, T::F32, T::F32, T::U1 )
OPCODE(FPCompare64, T::Void, T::F64, T::F64, T::U1 )
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
OPCODE(FPDiv32, T::F32, T::F32, T::F32 )
OPCODE(FPDiv64, T::F64, T::F64, T::F64 )
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
OPCODE(FPMul32, T::F32, T::F32, T::F32 )
OPCODE(FPMul64, T::F64, T::F64, T::F64 )
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
OPCODE(FPNeg32, T::F32, T::F32 )
OPCODE(FPNeg64, T::F64, T::F64 )
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
OPCODE(FPSqrt32, T::F32, T::F32 )
OPCODE(FPSqrt64, T::F64, T::F64 )
VFP: Implement VSUB
2016-08-07 01:41:25 +01:00
OPCODE(FPSub32, T::F32, T::F32, T::F32 )
OPCODE(FPSub64, T::F64, T::F64, T::F64 )
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point conversions
OPCODE(FPSingleToDouble, T::F64, T::F32 )
OPCODE(FPDoubleToSingle, T::F32, T::F64 )
OPCODE(FPSingleToU32, T::F32, T::F32, T::U1 )
OPCODE(FPSingleToS32, T::F32, T::F32, T::U1 )
OPCODE(FPDoubleToU32, T::F32, T::F64, T::U1 )
OPCODE(FPDoubleToS32, T::F32, T::F64, T::U1 )
OPCODE(FPU32ToSingle, T::F32, T::F32, T::U1 )
OPCODE(FPS32ToSingle, T::F32, T::F32, T::U1 )
OPCODE(FPU32ToDouble, T::F64, T::F32, T::U1 )
OPCODE(FPS32ToDouble, T::F64, T::F32, T::U1 )
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
// Memory access
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )
A32OPC(ReadMemory8, T::U8, T::U32 )
A32OPC(ReadMemory16, T::U16, T::U32 )
A32OPC(ReadMemory32, T::U32, T::U32 )
A32OPC(ReadMemory64, T::U64, T::U32 )
A32OPC(WriteMemory8, T::Void, T::U32, T::U8 )
A32OPC(WriteMemory16, T::Void, T::U32, T::U16 )
A32OPC(WriteMemory32, T::Void, T::U32, T::U32 )
A32OPC(WriteMemory64, T::Void, T::U32, T::U64 )
A32OPC(ExclusiveWriteMemory8, T::U32, T::U32, T::U8 )
A32OPC(ExclusiveWriteMemory16, T::U32, T::U32, T::U16 )
A32OPC(ExclusiveWriteMemory32, T::U32, T::U32, T::U32 )
A32OPC(ExclusiveWriteMemory64, T::U32, T::U32, T::U32, T::U32 )
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
// Coprocessor
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(CoprocInternalOperation, T::Void, T::CoprocInfo )
A32OPC(CoprocSendOneWord, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocSendTwoWords, T::Void, T::CoprocInfo, T::U32, T::U32 )
A32OPC(CoprocGetOneWord, T::U32, T::CoprocInfo )
A32OPC(CoprocGetTwoWords, T::U64, T::CoprocInfo )
A32OPC(CoprocLoadWords, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocStoreWords, T::Void, T::CoprocInfo, T::U32 )
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