2016-07-04 10:22:11 +01:00
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// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding
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// ARM instruction, and using the existing ARM simulator.
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2016-07-04 14:37:50 +01:00
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#include "skyeye_interpreter/dyncom/arm_dyncom_thumb.h"
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#include "skyeye_interpreter/skyeye_common/armsupp.h"
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2016-07-04 10:22:11 +01:00
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// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
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// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
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// allows easier simulation of the special dual BL instruction.
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ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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ThumbDecodeStatus valid = ThumbDecodeStatus::UNINITIALIZED;
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u32 tinstr = GetThumbInstruction(instr, addr);
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*ainstr = 0xDEADC0DE; // Debugging to catch non updates
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switch ((tinstr & 0xF800) >> 11) {
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case 0: // LSL
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case 1: // LSR
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case 2: // ASR
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*ainstr = 0xE1B00000 // base opcode
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| ((tinstr & 0x1800) >> (11 - 5)) // shift type
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|((tinstr & 0x07C0) << (7 - 6)) // imm5
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|((tinstr & 0x0038) >> 3) // Rs
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|((tinstr & 0x0007) << 12); // Rd
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break;
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case 3: // ADD/SUB
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{
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static const u32 subset[4] = {
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0xE0900000, // ADDS Rd,Rs,Rn
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0xE0500000, // SUBS Rd,Rs,Rn
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0xE2900000, // ADDS Rd,Rs,#imm3
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0xE2500000 // SUBS Rd,Rs,#imm3
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};
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// It is quicker indexing into a table, than performing switch or conditionals:
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*ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode
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|((tinstr & 0x01C0) >> 6) // Rn or imm3
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|((tinstr & 0x0038) << (16 - 3)) // Rs
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|((tinstr & 0x0007) << (12 - 0)); // Rd
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}
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break;
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case 4: // MOV
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case 5: // CMP
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case 6: // ADD
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case 7: // SUB
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{
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static const u32 subset[4] = {
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0xE3B00000, // MOVS Rd,#imm8
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0xE3500000, // CMP Rd,#imm8
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0xE2900000, // ADDS Rd,Rd,#imm8
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0xE2500000, // SUBS Rd,Rd,#imm8
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};
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*ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode
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|((tinstr & 0x00FF) >> 0) // imm8
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|((tinstr & 0x0700) << (16 - 8)) // Rn
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|((tinstr & 0x0700) << (12 - 8)); // Rd
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}
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break;
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case 8: // Arithmetic and high register transfers
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// TODO: Since the subsets for both Format 4 and Format 5 instructions are made up of
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// different ARM encodings, we could save the following conditional, and just have one
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// large subset
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if ((tinstr & (1 << 10)) == 0) {
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enum otype {
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t_norm,
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t_shift,
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t_neg,
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t_mul
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};
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static const struct {
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u32 opcode;
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otype type;
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} subset[16] = {
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{ 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs
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{ 0xE0300000, t_norm }, // EORS Rd,Rd,Rs
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{ 0xE1B00010, t_shift }, // MOVS Rd,Rd,LSL Rs
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{ 0xE1B00030, t_shift }, // MOVS Rd,Rd,LSR Rs
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{ 0xE1B00050, t_shift }, // MOVS Rd,Rd,ASR Rs
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{ 0xE0B00000, t_norm }, // ADCS Rd,Rd,Rs
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{ 0xE0D00000, t_norm }, // SBCS Rd,Rd,Rs
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{ 0xE1B00070, t_shift }, // MOVS Rd,Rd,ROR Rs
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{ 0xE1100000, t_norm }, // TST Rd,Rs
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{ 0xE2700000, t_neg }, // RSBS Rd,Rs,#0
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{ 0xE1500000, t_norm }, // CMP Rd,Rs
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{ 0xE1700000, t_norm }, // CMN Rd,Rs
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{ 0xE1900000, t_norm }, // ORRS Rd,Rd,Rs
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{ 0xE0100090, t_mul }, // MULS Rd,Rd,Rs
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{ 0xE1D00000, t_norm }, // BICS Rd,Rd,Rs
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{ 0xE1F00000, t_norm } // MVNS Rd,Rs
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};
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*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base
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switch (subset[(tinstr & 0x03C0) >> 6].type) {
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case t_norm:
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*ainstr |= ((tinstr & 0x0007) << 16) // Rn
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|((tinstr & 0x0007) << 12) // Rd
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|((tinstr & 0x0038) >> 3); // Rs
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break;
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case t_shift:
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*ainstr |= ((tinstr & 0x0007) << 12) // Rd
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|((tinstr & 0x0007) >> 0) // Rm
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|((tinstr & 0x0038) << (8 - 3)); // Rs
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break;
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case t_neg:
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*ainstr |= ((tinstr & 0x0007) << 12) // Rd
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|((tinstr & 0x0038) << (16 - 3)); // Rn
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break;
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case t_mul:
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*ainstr |= ((tinstr & 0x0007) << 16) // Rd
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|((tinstr & 0x0007) << 8) // Rs
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|((tinstr & 0x0038) >> 3); // Rm
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break;
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}
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} else {
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u32 Rd = ((tinstr & 0x0007) >> 0);
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u32 Rs = ((tinstr & 0x0078) >> 3);
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if (tinstr & (1 << 7))
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Rd += 8;
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switch ((tinstr & 0x03C0) >> 6) {
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case 0x0: // ADD Rd,Rd,Rs
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case 0x1: // ADD Rd,Rd,Hs
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case 0x2: // ADD Hd,Hd,Rs
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case 0x3: // ADD Hd,Hd,Hs
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*ainstr = 0xE0800000 // base
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| (Rd << 16) // Rn
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|(Rd << 12) // Rd
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|(Rs << 0); // Rm
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break;
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case 0x4: // CMP Rd,Rs
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case 0x5: // CMP Rd,Hs
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case 0x6: // CMP Hd,Rs
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case 0x7: // CMP Hd,Hs
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*ainstr = 0xE1500000 // base
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| (Rd << 16) // Rn
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|(Rs << 0); // Rm
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break;
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case 0x8: // MOV Rd,Rs
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case 0x9: // MOV Rd,Hs
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case 0xA: // MOV Hd,Rs
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case 0xB: // MOV Hd,Hs
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*ainstr = 0xE1A00000 // base
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|(Rd << 12) // Rd
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|(Rs << 0); // Rm
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break;
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case 0xC: // BX Rs
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case 0xD: // BX Hs
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*ainstr = 0xE12FFF10 // base
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| ((tinstr & 0x0078) >> 3); // Rd
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break;
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case 0xE: // BLX
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case 0xF: // BLX
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*ainstr = 0xE1200030 // base
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| (Rs << 0); // Rm
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break;
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}
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}
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break;
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case 9: // LDR Rd,[PC,#imm8]
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*ainstr = 0xE59F0000 // base
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| ((tinstr & 0x0700) << (12 - 8)) // Rd
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|((tinstr & 0x00FF) << (2 - 0)); // off8
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break;
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case 10:
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case 11:
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{
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static const u32 subset[8] = {
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0xE7800000, // STR Rd,[Rb,Ro]
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0xE18000B0, // STRH Rd,[Rb,Ro]
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0xE7C00000, // STRB Rd,[Rb,Ro]
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0xE19000D0, // LDRSB Rd,[Rb,Ro]
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0xE7900000, // LDR Rd,[Rb,Ro]
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0xE19000B0, // LDRH Rd,[Rb,Ro]
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0xE7D00000, // LDRB Rd,[Rb,Ro]
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0xE19000F0 // LDRSH Rd,[Rb,Ro]
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};
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*ainstr = subset[(tinstr & 0xE00) >> 9] // base
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|((tinstr & 0x0007) << (12 - 0)) // Rd
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|((tinstr & 0x0038) << (16 - 3)) // Rb
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|((tinstr & 0x01C0) >> 6); // Ro
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}
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break;
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case 12: // STR Rd,[Rb,#imm5]
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case 13: // LDR Rd,[Rb,#imm5]
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case 14: // STRB Rd,[Rb,#imm5]
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case 15: // LDRB Rd,[Rb,#imm5]
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{
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static const u32 subset[4] = {
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0xE5800000, // STR Rd,[Rb,#imm5]
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0xE5900000, // LDR Rd,[Rb,#imm5]
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0xE5C00000, // STRB Rd,[Rb,#imm5]
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0xE5D00000 // LDRB Rd,[Rb,#imm5]
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};
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// The offset range defends on whether we are transferring a byte or word value:
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*ainstr = subset[(tinstr & 0x1800) >> 11] // base
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|((tinstr & 0x0007) << (12 - 0)) // Rd
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|((tinstr & 0x0038) << (16 - 3)) // Rb
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|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5
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}
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break;
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case 16: // STRH Rd,[Rb,#imm5]
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case 17: // LDRH Rd,[Rb,#imm5]
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*ainstr = ((tinstr & (1 << 11)) // base
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? 0xE1D000B0 // LDRH
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: 0xE1C000B0) // STRH
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|((tinstr & 0x0007) << (12 - 0)) // Rd
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|((tinstr & 0x0038) << (16 - 3)) // Rb
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|((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble
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|((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble
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break;
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case 18: // STR Rd,[SP,#imm8]
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case 19: // LDR Rd,[SP,#imm8]
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*ainstr = ((tinstr & (1 << 11)) // base
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? 0xE59D0000 // LDR
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: 0xE58D0000) // STR
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|((tinstr & 0x0700) << (12 - 8)) // Rd
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|((tinstr & 0x00FF) << 2); // off8
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break;
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case 20: // ADD Rd,PC,#imm8
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case 21: // ADD Rd,SP,#imm8
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if ((tinstr & (1 << 11)) == 0) {
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// NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the
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// rotate immediate field, so no shift of off8 is needed.
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*ainstr = 0xE28F0F00 // base
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| ((tinstr & 0x0700) << (12 - 8)) // Rd
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|(tinstr & 0x00FF); // off8
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} else {
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// We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed.
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*ainstr = 0xE28D0F00 // base
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| ((tinstr & 0x0700) << (12 - 8)) // Rd
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|(tinstr & 0x00FF); // off8
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}
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break;
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case 22:
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case 23:
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if ((tinstr & 0x0F00) == 0x0000) {
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// NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30):
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*ainstr = ((tinstr & (1 << 7)) // base
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? 0xE24DDF00 // SUB
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: 0xE28DDF00) // ADD
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|(tinstr & 0x007F); // off7
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} else if ((tinstr & 0x0F00) == 0x0e00) {
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// BKPT
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*ainstr = 0xEF000000 // base
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| BITS(tinstr, 0, 3) // imm4 field;
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| (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12
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} else if ((tinstr & 0x0F00) == 0x0200) {
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static const u32 subset[4] = {
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0xE6BF0070, // SXTH
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0xE6AF0070, // SXTB
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0xE6FF0070, // UXTH
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0xE6EF0070, // UXTB
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};
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*ainstr = subset[BITS(tinstr, 6, 7)] // base
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| (BITS(tinstr, 0, 2) << 12) // Rd
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| BITS(tinstr, 3, 5); // Rm
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} else if ((tinstr & 0x0F00) == 0x600) {
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if (BIT(tinstr, 5) == 0) {
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// SETEND
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*ainstr = 0xF1010000 // base
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| (BIT(tinstr, 3) << 9); // endian specifier
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} else {
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// CPS
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*ainstr = 0xF1080000 // base
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| (BIT(tinstr, 0) << 6) // fiq bit
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| (BIT(tinstr, 1) << 7) // irq bit
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| (BIT(tinstr, 2) << 8) // abort bit
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| (BIT(tinstr, 4) << 18); // enable bit
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}
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} else if ((tinstr & 0x0F00) == 0x0a00) {
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2016-07-16 19:22:09 +01:00
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static const u32 subset[4] = {
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2016-07-04 10:22:11 +01:00
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0xE6BF0F30, // REV
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0xE6BF0FB0, // REV16
|
2016-07-16 19:22:09 +01:00
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0, // undefined
|
2016-07-04 10:22:11 +01:00
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|
0xE6FF0FB0, // REVSH
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};
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|
2016-07-16 19:22:09 +01:00
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|
size_t subset_index = BITS(tinstr, 6, 7);
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|
|
|
|
|
if (subset_index == 2) {
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|
valid = ThumbDecodeStatus::UNDEFINED;
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|
|
} else {
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|
*ainstr = subset[subset_index] // base
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| (BITS(tinstr, 0, 2) << 12) // Rd
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| BITS(tinstr, 3, 5); // Rm
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|
|
}
|
2016-07-04 10:22:11 +01:00
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|
|
} else {
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|
|
static const u32 subset[4] = {
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|
|
0xE92D0000, // STMDB sp!,{rlist}
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|
0xE92D4000, // STMDB sp!,{rlist,lr}
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|
0xE8BD0000, // LDMIA sp!,{rlist}
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|
0xE8BD8000 // LDMIA sp!,{rlist,pc}
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|
};
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*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] // base
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|(tinstr & 0x00FF); // mask8
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|
}
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|
break;
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|
|
case 24: // STMIA
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|
case 25: // LDMIA
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|
|
if (tinstr & (1 << 11))
|
|
|
|
|
{
|
|
|
|
|
unsigned int base = 0xE8900000;
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|
|
|
|
unsigned int rn = BITS(tinstr, 8, 10);
|
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|
|
|
|
|
|
// Writeback
|
|
|
|
|
if ((tinstr & (1 << rn)) == 0)
|
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|
|
base |= (1 << 21);
|
|
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|
|
|
|
|
|
|
*ainstr = base // base (LDMIA)
|
|
|
|
|
| (rn << 16) // Rn
|
|
|
|
|
| (tinstr & 0x00FF); // Register list
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
*ainstr = 0xE8A00000 // base (STMIA)
|
|
|
|
|
| (BITS(tinstr, 8, 10) << 16) // Rn
|
|
|
|
|
| (tinstr & 0x00FF); // Register list
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 26: // Bcc
|
|
|
|
|
case 27: // Bcc/SWI
|
|
|
|
|
if ((tinstr & 0x0F00) == 0x0F00) {
|
|
|
|
|
// Format 17 : SWI
|
|
|
|
|
*ainstr = 0xEF000000;
|
|
|
|
|
// Breakpoint must be handled specially.
|
|
|
|
|
if ((tinstr & 0x00FF) == 0x18)
|
|
|
|
|
*ainstr |= ((tinstr & 0x00FF) << 16);
|
|
|
|
|
// New breakpoint value. See gdb/arm-tdep.c
|
|
|
|
|
else if ((tinstr & 0x00FF) == 0xFE)
|
|
|
|
|
*ainstr |= 0x180000; // base |= BKPT mask
|
|
|
|
|
else
|
|
|
|
|
*ainstr |= (tinstr & 0x00FF);
|
|
|
|
|
} else if ((tinstr & 0x0F00) != 0x0E00)
|
|
|
|
|
valid = ThumbDecodeStatus::BRANCH;
|
|
|
|
|
else // UNDEFINED : cc=1110(AL) uses different format
|
|
|
|
|
valid = ThumbDecodeStatus::UNDEFINED;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 28: // B
|
|
|
|
|
valid = ThumbDecodeStatus::BRANCH;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 29:
|
|
|
|
|
if (tinstr & 0x1)
|
|
|
|
|
valid = ThumbDecodeStatus::UNDEFINED;
|
|
|
|
|
else
|
|
|
|
|
valid = ThumbDecodeStatus::BRANCH;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 30: // BL instruction 1
|
|
|
|
|
|
|
|
|
|
// There is no single ARM instruction equivalent for this Thumb instruction. To keep the
|
|
|
|
|
// simulation simple (from the user perspective) we check if the following instruction is
|
|
|
|
|
// the second half of this BL, and if it is we simulate it immediately
|
|
|
|
|
|
|
|
|
|
valid = ThumbDecodeStatus::BRANCH;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 31: // BL instruction 2
|
|
|
|
|
|
|
|
|
|
// There is no single ARM instruction equivalent for this instruction. Also, it should only
|
|
|
|
|
// ever be matched with the fmt19 "BL instruction 1" instruction. However, we do allow the
|
|
|
|
|
// simulation of it on its own, with undefined results if r14 is not suitably initialised.
|
|
|
|
|
|
|
|
|
|
valid = ThumbDecodeStatus::BRANCH;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*inst_size = 2;
|
|
|
|
|
|
|
|
|
|
return valid;
|
|
|
|
|
}
|
