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A64: Implement URSQRTE

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Lioncash 2018-09-08 00:03:40 -04:00 committed by MerryMage
parent b6e74fd17d
commit 0a3976059f
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -652,7 +652,7 @@ INST(FCMLE_4, "FCMLE (zero)", "0Q101
INST(FCVTPU_4, "FCVTPU (vector)", "0Q1011101z100001101010nnnnnddddd")
//INST(FCVTZU_int_3, "FCVTZU (vector, integer)", "0Q10111011111001101110nnnnnddddd")
INST(FCVTZU_int_4, "FCVTZU (vector, integer)", "0Q1011101z100001101110nnnnnddddd")
//INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd")
INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd")
//INST(FRSQRTE_3, "FRSQRTE", "0Q10111011111001110110nnnnnddddd")
INST(FRSQRTE_4, "FRSQRTE", "0Q1011101z100001110110nnnnnddddd")
//INST(FSQRT_1, "FSQRT (vector)", "0Q10111011111001111110nnnnnddddd")

14
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -659,6 +659,20 @@ bool TranslatorVisitor::URECPE(bool Q, bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.VectorUnsignedRecipSqrtEstimate(operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed);
}