From 15b3de95e44ef3d63241b009219789506cde959b Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 15 Jun 2020 18:25:52 -0400 Subject: [PATCH] A32: Implement VNEG --- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_misc.cpp | 26 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 4e9f870f..a53c2c09 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -93,7 +93,7 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001 //INST(asimd_VCLE_zero, "VCLE (zero)", "111100111-11--01----0x011x-0----") // ASIMD //INST(asimd_VCLT_zero, "VCLT (zero)", "111100111-11--01----0x100x-0----") // ASIMD //INST(asimd_VABS, "VABS", "111100111-11--01----0x110x-0----") // ASIMD -//INST(asimd_VNEG, "VNEG", "111100111-11--01----0x111x-0----") // ASIMD +INST(asimd_VNEG, "VNEG", "111100111D11zz01dddd0F111QM0mmmm") // ASIMD INST(asimd_VSWP, "VSWP", "111100111D110010dddd00000QM0mmmm") // ASIMD //INST(asimd_VTRN, "VTRN", "111100111-11--10----00001x-0----") // ASIMD //INST(asimd_VUZP, "VUZP", "111100111-11--10----00010x-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index ba008f16..6a00b1e0 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -9,6 +9,32 @@ namespace Dynarmic::A32 { +bool ArmTranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { + if (sz == 0b11 || (F && sz != 0b10)) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto result = [this, F, m, sz] { + const auto reg_m = ir.GetVector(m); + + if (F) { + return ir.FPVectorNeg(32, reg_m); + } + + const size_t esize = 8U << sz; + return ir.VectorSub(esize, ir.ZeroVector(), reg_m); + }(); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 745010e3..39f214f9 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -449,6 +449,7 @@ struct ArmTranslatorVisitor final { bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); // Advanced SIMD two register, miscellaneous + bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); // Advanced SIMD load/store structures