From 3f93c77ace45df8298735dee8571a7345cb634f3 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 10 Feb 2018 11:12:54 +0000 Subject: [PATCH] A64: Implement SIMD instruction USRA, vector variant --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_shift_by_immediate.cpp | 21 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 8e74dffc..3e773138 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -792,7 +792,7 @@ INST(SHL_2, "SHL", "0Q001 //INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd") //INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd") INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd") -//INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd") +INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd") //INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd") //INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd") //INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 072f53f7..55627710 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -47,6 +47,27 @@ bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return true; } +bool TranslatorVisitor::USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (immh == 0b0000) { + return DecodeError(); + } + if (immh.Bit<3>() && !Q) { + return ReservedValue(); + } + const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t datasize = Q ? 128 : 64; + + const u8 shift_amount = static_cast(2 * esize) - concatenate(immh, immb).ZeroExtend(); + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vd); + const IR::U128 shifted_operand = ir.VectorLogicalShiftRight(esize, operand, shift_amount); + const IR::U128 result = ir.VectorAdd(esize, shifted_operand, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (immh == 0b0000) { return DecodeError();