From 589ad7232f5e7f274f985f6e641e803618289029 Mon Sep 17 00:00:00 2001 From: James Rowe Date: Tue, 23 Jan 2018 22:16:07 -0700 Subject: [PATCH] Fixup: Xn|SP are 64 bit addresses encoded in the Rn field --- .../impl/load_store_register_unprivileged.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/frontend/A64/translate/impl/load_store_register_unprivileged.cpp b/src/frontend/A64/translate/impl/load_store_register_unprivileged.cpp index c3e2d4a8..df90f7f3 100644 --- a/src/frontend/A64/translate/impl/load_store_register_unprivileged.cpp +++ b/src/frontend/A64/translate/impl/load_store_register_unprivileged.cpp @@ -17,9 +17,9 @@ static bool StoreRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t dat if (Rn == Reg::SP) { // TODO: Check Stack Alignment - address = tv.SP(datasize); + address = tv.SP(64); } else { - address = tv.X(datasize, Rn); + address = tv.X(64, Rn); } address = ir.Add(address, ir.Imm64(offset)); IR::UAny data = tv.X(datasize, Rt); @@ -35,9 +35,9 @@ static bool LoadRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t data if (Rn == Reg::SP) { // TODO: Check Stack Alignment - address = tv.SP(datasize); + address = tv.SP(64); } else { - address = tv.X(datasize, Rn); + address = tv.X(64, Rn); } address = ir.Add(address, ir.Imm64(offset)); IR::UAny data = tv.Mem(address, datasize / 8, acctype); @@ -69,9 +69,9 @@ static bool LoadRegisterSigned(TranslatorVisitor& tv, IREmitter& ir, const size_ IR::U64 address; if (Rn == Reg::SP) { // TODO: Check Stack Alignment - address = tv.SP(datasize); + address = tv.SP(64); } else { - address = tv.X(datasize, Rn); + address = tv.X(64, Rn); } address = ir.Add(address, ir.Imm64(offset));