ir: Add opcodes for floating-point vector equalities
This commit is contained in:
parent
e64978ed89
commit
5ce187a54e
4 changed files with 34 additions and 0 deletions
|
@ -189,6 +189,26 @@ void EmitX64::EmitFPVectorDiv64(EmitContext& ctx, IR::Inst* inst) {
|
||||||
EmitVectorOperation64(code, ctx, inst, &Xbyak::CodeGenerator::divpd);
|
EmitVectorOperation64(code, ctx, inst, &Xbyak::CodeGenerator::divpd);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void EmitX64::EmitFPVectorEqual32(EmitContext& ctx, IR::Inst* inst) {
|
||||||
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||||
|
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||||
|
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
|
||||||
|
|
||||||
|
code.cmpeqps(a, b);
|
||||||
|
|
||||||
|
ctx.reg_alloc.DefineValue(inst, a);
|
||||||
|
}
|
||||||
|
|
||||||
|
void EmitX64::EmitFPVectorEqual64(EmitContext& ctx, IR::Inst* inst) {
|
||||||
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||||
|
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||||
|
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
|
||||||
|
|
||||||
|
code.cmpeqpd(a, b);
|
||||||
|
|
||||||
|
ctx.reg_alloc.DefineValue(inst, a);
|
||||||
|
}
|
||||||
|
|
||||||
void EmitX64::EmitFPVectorMul32(EmitContext& ctx, IR::Inst* inst) {
|
void EmitX64::EmitFPVectorMul32(EmitContext& ctx, IR::Inst* inst) {
|
||||||
EmitVectorOperation32(code, ctx, inst, &Xbyak::CodeGenerator::mulps);
|
EmitVectorOperation32(code, ctx, inst, &Xbyak::CodeGenerator::mulps);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1503,6 +1503,17 @@ U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b) {
|
||||||
return {};
|
return {};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) {
|
||||||
|
switch (esize) {
|
||||||
|
case 32:
|
||||||
|
return Inst<U128>(Opcode::FPVectorEqual32, a, b);
|
||||||
|
case 64:
|
||||||
|
return Inst<U128>(Opcode::FPVectorEqual64, a, b);
|
||||||
|
}
|
||||||
|
UNREACHABLE();
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) {
|
U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) {
|
||||||
switch (esize) {
|
switch (esize) {
|
||||||
case 32:
|
case 32:
|
||||||
|
|
|
@ -274,6 +274,7 @@ public:
|
||||||
|
|
||||||
U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
|
U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
|
||||||
U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);
|
U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);
|
||||||
|
U128 FPVectorEqual(size_t esize, const U128& a, const U128& b);
|
||||||
U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
|
U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
|
||||||
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
|
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
|
||||||
U128 FPVectorS32ToSingle(const U128& a);
|
U128 FPVectorS32ToSingle(const U128& a);
|
||||||
|
|
|
@ -398,6 +398,8 @@ OPCODE(FPVectorAdd32, T::U128, T::U128, T::U
|
||||||
OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 )
|
OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 )
|
||||||
OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 )
|
OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 )
|
||||||
OPCODE(FPVectorDiv64, T::U128, T::U128, T::U128 )
|
OPCODE(FPVectorDiv64, T::U128, T::U128, T::U128 )
|
||||||
|
OPCODE(FPVectorEqual32, T::U128, T::U128, T::U128 )
|
||||||
|
OPCODE(FPVectorEqual64, T::U128, T::U128, T::U128 )
|
||||||
OPCODE(FPVectorMul32, T::U128, T::U128, T::U128 )
|
OPCODE(FPVectorMul32, T::U128, T::U128, T::U128 )
|
||||||
OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 )
|
OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 )
|
||||||
OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )
|
OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )
|
||||||
|
|
Loading…
Reference in a new issue