From 603cd09c8f49b12e8480f39166addcae16755a04 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 11:44:27 +0100 Subject: [PATCH] A32: Implement ASIMD VTRN --- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_misc.cpp | 27 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 5ce0c56b..2daf856c 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -99,7 +99,7 @@ INST(asimd_VCLT_zero, "VCLT (zero)", "111100111D11zz01dddd0F1 INST(asimd_VABS, "VABS", "111100111D11zz01dddd0F110QM0mmmm") // ASIMD INST(asimd_VNEG, "VNEG", "111100111D11zz01dddd0F111QM0mmmm") // ASIMD INST(asimd_VSWP, "VSWP", "111100111D110010dddd00000QM0mmmm") // ASIMD -//INST(asimd_VTRN, "VTRN", "111100111-11--10----00001x-0----") // ASIMD +INST(asimd_VTRN, "VTRN", "111100111D11zz10dddd00001QM0mmmm") // ASIMD //INST(asimd_VUZP, "VUZP", "111100111-11--10----00010x-0----") // ASIMD //INST(asimd_VZIP, "VZIP", "111100111-11--10----00011x-0----") // ASIMD //INST(asimd_VMOVN, "VMOVN", "111100111-11--10----001000-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index c1764caa..c9c08e4c 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -397,6 +397,33 @@ bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t return true; } +bool ArmTranslatorVisitor::asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz == 0b11) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + + if (d == m) { + return UnpredictableInstruction(); + } + + const auto reg_d = ir.GetVector(d); + const auto reg_m = ir.GetVector(m); + const auto result_d = ir.VectorTranspose(esize, reg_d, reg_m, false); + const auto result_m = ir.VectorTranspose(esize, reg_d, reg_m, true); + + ir.SetVector(d, result_d); + ir.SetVector(m, result_m); + return true; +} + bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 940a88f9..83f88ca9 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -527,6 +527,7 @@ struct ArmTranslatorVisitor final { bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);