From 7aeaa46a0b75df93284395005e0f5255e392fa8b Mon Sep 17 00:00:00 2001
From: Merry <git@mary.rs>
Date: Tue, 26 Jul 2022 09:07:48 +0100
Subject: [PATCH] emit_arm64_packed: Implement PackedAddS16

---
 .../backend/arm64/emit_arm64_packed.cpp       | 21 +++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
index e547e7c2..9cc4bd44 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
@@ -97,10 +97,23 @@ void EmitIR<IR::Opcode::PackedAddU16>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::PackedAddS16>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    const auto ge_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetGEFromOp);
+
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    auto Vresult = ctx.reg_alloc.WriteD(inst);
+    auto Va = ctx.reg_alloc.ReadD(args[0]);
+    auto Vb = ctx.reg_alloc.ReadD(args[1]);
+    RegAlloc::Realize(Vresult, Va, Vb);
+
+    code.ADD(Vresult->H4(), Va->H4(), Vb->H4());
+
+    if (ge_inst) {
+        auto Vge = ctx.reg_alloc.WriteD(ge_inst);
+        RegAlloc::Realize(Vge);
+
+        code.SHADD(Vge->H4(), Va->H4(), Vb->H4());
+        code.CMGE(Vge->H4(), Vge->H4(), 0);
+    }
 }
 
 template<>