diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 96a672ff..5ce2c2e7 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -410,7 +410,7 @@ INST(UCVTF_int_2, "UCVTF (vector, integer)", "01111 INST(CMGT_zero_1, "CMGT (zero)", "01011110zz100000100010nnnnnddddd") INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd") //INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd") -//INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd") +INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd") //INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd") //INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd") //INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index 559732a7..e4c102e5 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -8,6 +8,19 @@ namespace Dynarmic::A64 { +bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) { + if (size != 0b11) { + return ReservedValue(); + } + + const IR::U64 operand1 = V_scalar(64, Vn); + const IR::U64 operand2 = ir.ArithmeticShiftRight(operand1, ir.Imm8(63)); + const IR::U64 result = ir.Sub(ir.Eor(operand1, operand2), operand2); + + V_scalar(64, Vd, result); + return true; +} + bool TranslatorVisitor::NEG_1(Imm<2> size, Vec Vn, Vec Vd) { if (size != 0b11) { return ReservedValue();