diff --git a/src/backend/x64/emit_x64_vector_floating_point.cpp b/src/backend/x64/emit_x64_vector_floating_point.cpp index b72414fa..aa2cd25d 100644 --- a/src/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/backend/x64/emit_x64_vector_floating_point.cpp @@ -1176,6 +1176,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in if constexpr (fsize != 16) { if (code.HasFMA() && code.HasAVX()) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const bool fpcr_controlled = args[2].GetImmediateU1(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]); @@ -1184,8 +1185,10 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in Xbyak::Label end, fallback; - code.movaps(result, GetVectorOf(code)); - FCODE(vfnmadd231p)(result, operand1, operand2); + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + code.movaps(result, GetVectorOf(code)); + FCODE(vfnmadd231p)(result, operand1, operand2); + }); FCODE(vcmpunordp)(tmp, result, result); code.vptest(tmp, tmp); @@ -1196,7 +1199,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in code.L(fallback); code.sub(rsp, 8); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); - EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn); + EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn, fpcr_controlled); ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx())); code.add(rsp, 8); code.jmp(end, code.T_NEAR); @@ -1207,7 +1210,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in } } - EmitThreeOpFallback(code, ctx, inst, fallback_fn); + EmitThreeOpFallback(code, ctx, inst, fallback_fn); } void EmitX64::EmitFPVectorRecipStepFused16(EmitContext& ctx, IR::Inst* inst) { diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index a1c0cf31..7ab66c1a 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -46,7 +46,7 @@ INST(asimd_VMUL_float, "VMUL (floating-point)", "111100110D0znnnndddd110 //INST(asimd_VACGE, "VACGE", "111100110-CC--------1110---1----") // ASIMD INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD -//INST(asimd_VRECPS, "VRECPS", "111100100-0C--------1111---1----") // ASIMD +INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm") // ASIMD //INST(asimd_VRSQRTS, "VRSQRTS", "111100100-1C--------1111---1----") // ASIMD // Two registers and a scalar diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp index e49d5dcf..8d45594d 100644 --- a/src/frontend/A32/translate/impl/asimd_three_same.cpp +++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp @@ -413,4 +413,10 @@ bool ArmTranslatorVisitor::asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t V }); } +bool ArmTranslatorVisitor::asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { + return ir.FPVectorRecipStepFused(32, reg_n, reg_m, false); + }); +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 71a98526..14c085b7 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -471,6 +471,7 @@ struct ArmTranslatorVisitor final { bool asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); // Two registers and a shift amount bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 04c03970..42c2ebc8 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -2452,14 +2452,14 @@ U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) { UNREACHABLE(); } -U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) { +U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) { switch (esize) { case 16: - return Inst(Opcode::FPVectorRecipStepFused16, a, b); + return Inst(Opcode::FPVectorRecipStepFused16, a, b, Imm1(fpcr_controlled)); case 32: - return Inst(Opcode::FPVectorRecipStepFused32, a, b); + return Inst(Opcode::FPVectorRecipStepFused32, a, b, Imm1(fpcr_controlled)); case 64: - return Inst(Opcode::FPVectorRecipStepFused64, a, b); + return Inst(Opcode::FPVectorRecipStepFused64, a, b, Imm1(fpcr_controlled)); } UNREACHABLE(); } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index f3ad48d6..ec4312cb 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -361,7 +361,7 @@ public: U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRecipEstimate(size_t esize, const U128& a); - U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b); + U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact); U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 0098f1d2..f1d2bb72 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -616,9 +616,9 @@ OPCODE(FPVectorPairedAddLower64, U128, U128 OPCODE(FPVectorRecipEstimate16, U128, U128 ) OPCODE(FPVectorRecipEstimate32, U128, U128 ) OPCODE(FPVectorRecipEstimate64, U128, U128 ) -OPCODE(FPVectorRecipStepFused16, U128, U128, U128 ) -OPCODE(FPVectorRecipStepFused32, U128, U128, U128 ) -OPCODE(FPVectorRecipStepFused64, U128, U128, U128 ) +OPCODE(FPVectorRecipStepFused16, U128, U128, U128, U1 ) +OPCODE(FPVectorRecipStepFused32, U128, U128, U128, U1 ) +OPCODE(FPVectorRecipStepFused64, U128, U128, U128, U1 ) OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt32, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt64, U128, U128, U8, U1 )