diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index e1d9d54a..429fc207 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -644,7 +644,7 @@ INST(XTN,                    "XTN, XTN2",                                 "0Q001
 //INST(CLZ_asimd,              "CLZ (vector)",                              "0Q101110zz100000010010nnnnnddddd")
 //INST(UADALP,                 "UADALP",                                    "0Q101110zz100000011010nnnnnddddd")
 //INST(SHLL,                   "SHLL, SHLL2",                               "0Q101110zz100001001110nnnnnddddd")
-//INST(NOT,                    "NOT",                                       "0Q10111000100000010110nnnnnddddd")
+INST(NOT,                    "NOT",                                       "0Q10111000100000010110nnnnnddddd")
 //INST(RBIT_asimd,             "RBIT (vector)",                             "0Q10111001100000010110nnnnnddddd")
 //INST(URSQRTE,                "URSQRTE",                                   "0Q1011101z100001110010nnnnnddddd")
 
diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index 27cf3c40..160c39bb 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -36,4 +36,18 @@ bool TranslatorVisitor::XTN(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::NOT(bool Q, Vec Vn, Vec Vd) {
+    const size_t datasize = Q ? 128 : 64;
+
+    const IR::U128 operand = V(datasize, Vn);
+    IR::U128 result = ir.VectorNot(operand);
+
+    if (datasize == 64) {
+        result = ir.VectorZeroUpper(result);
+    }
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 } // namespace Dynarmic::A64