From bc6016cad76deba38e35fbc9ee1d4aeb54ceb8f4 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sat, 7 Apr 2018 21:04:29 -0400
Subject: [PATCH] A64: Implement SRSHR (vector)

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../impl/simd_shift_by_immediate.cpp          | 35 +++++++++++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 0ba1228c..e8a306f8 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -791,7 +791,7 @@ INST(UnallocatedEncoding,    "Unallocated SIMD modified immediate",       "0--01
 // Data Processing - FP and SIMD - SIMD Shift by immediate
 INST(SSHR_2,                 "SSHR",                                      "0Q0011110IIIIiii000001nnnnnddddd")
 INST(SSRA_2,                 "SSRA",                                      "0Q0011110IIIIiii000101nnnnnddddd")
-//INST(SRSHR_2,                "SRSHR",                                     "0Q0011110IIIIiii001001nnnnnddddd")
+INST(SRSHR_2,                "SRSHR",                                     "0Q0011110IIIIiii001001nnnnnddddd")
 //INST(SRSRA_2,                "SRSRA",                                     "0Q0011110IIIIiii001101nnnnnddddd")
 INST(SHL_2,                  "SHL",                                       "0Q0011110IIIIiii010101nnnnnddddd")
 //INST(SQSHL_imm_2,            "SQSHL (immediate)",                         "0Q0011110IIIIiii011101nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
index 9f38b5f7..8bba5924 100644
--- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
+++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
@@ -45,6 +45,41 @@ bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
     return true;
 }
 
+static void SignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
+                                     ShiftExtraBehavior behavior) {
+    const size_t datasize = Q ? 128 : 64;
+    const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
+    const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
+    const u64 round_value = 1ULL << (shift_amount - 1);
+
+    const IR::U128 operand = v.V(datasize, Vn);
+    const IR::U128 round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
+    const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const);
+
+    const IR::U128 result = v.ir.VectorArithmeticShiftRight(esize, operand, shift_amount);
+    IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction);
+
+    if (behavior == ShiftExtraBehavior::Accumulate) {
+        const IR::U128 accumulator = v.V(datasize, Vd);
+        corrected_result = v.ir.VectorAdd(esize, accumulator, corrected_result);
+    }
+
+    v.V(datasize, Vd, corrected_result);
+}
+
+bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
+    if (immh == 0b0000) {
+        return DecodeError();
+    }
+
+    if (!Q && immh.Bit<3>()) {
+        return ReservedValue();
+    }
+
+    SignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
+    return true;
+}
+
 bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
     if (immh == 0b0000) {
         return DecodeError();