diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 71579228..066d7e8f 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -779,7 +779,7 @@ INST(MOVI, "MOVI, MVNI, ORR, BIC (vector, immediate)", "0Qo01 // Data Processing - FP and SIMD - SIMD Shift by immediate INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd") -//INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd") +INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd") //INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd") //INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd") INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 62647d47..a06c4c74 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -28,6 +28,27 @@ bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return true; } +bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (immh == 0b0000) { + return DecodeError(); + } + if (immh.Bit<3>() && !Q) { + return ReservedValue(); + } + const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t datasize = Q ? 128 : 64; + + const u8 shift_amount = static_cast(2 * esize) - concatenate(immh, immb).ZeroExtend(); + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vd); + const IR::U128 shifted_operand = ir.VectorArithmeticShiftRight(esize, operand, shift_amount); + const IR::U128 result = ir.VectorAdd(esize, shifted_operand, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (immh == 0b0000) { return DecodeError();