From ccf7df057b12daceaccc58b7af8db80b5111c399 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 13 Feb 2018 19:01:47 +0000 Subject: [PATCH] simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) --- src/frontend/A64/translate/impl/simd_three_same.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index db022413..0b4b3030 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -27,7 +27,10 @@ bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(datasize, Vm); - const IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2); + IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2); + if (datasize == 64) { + result = ir.VectorZeroUpper(result); + } V(datasize, Vd, result); return true; } @@ -188,7 +191,10 @@ bool TranslatorVisitor::CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(datasize, Vm); - const IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2); + IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2); + if (datasize == 64) { + result = ir.VectorZeroUpper(result); + } V(datasize, Vd, result); return true; }