A32: Implement ARMv8 VST{1-4} (multiple)
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eb332b3836
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6 changed files with 122 additions and 80 deletions
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@ -121,7 +121,7 @@ INST(asimd_VBIF, "VBIF", "111100110D11nnnndddd000
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----11100-11efgh") // ASIMD
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----11100-11efgh") // ASIMD
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// Advanced SIMD load/store structures
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// Advanced SIMD load/store structures
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//INST(v8_VST_multiple, "VST{1-4} (multiple)", "111101000D00nnnnddddxxxxzzaammmm") // v8
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INST(v8_VST_multiple, "VST{1-4} (multiple)", "111101000D00nnnnddddxxxxzzaammmm") // v8
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INST(v8_VLD_multiple, "VLD{1-4} (multiple)", "111101000D10nnnnddddxxxxzzaammmm") // v8
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INST(v8_VLD_multiple, "VLD{1-4} (multiple)", "111101000D10nnnnddddxxxxzzaammmm") // v8
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INST(arm_UDF, "UNALLOCATED", "111101000--0--------1011--------") // v8
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INST(arm_UDF, "UNALLOCATED", "111101000--0--------1011--------") // v8
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INST(arm_UDF, "UNALLOCATED", "111101000--0--------11----------") // v8
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INST(arm_UDF, "UNALLOCATED", "111101000--0--------11----------") // v8
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@ -5,107 +5,129 @@
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#include "frontend/A32/translate/impl/translate_arm.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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#include <optional>
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#include <tuple>
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#include "common/bit_util.h"
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#include "common/bit_util.h"
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namespace Dynarmic::A32 {
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namespace Dynarmic::A32 {
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static ExtReg ToExtRegD(size_t base, bool bit) {
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namespace {
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ExtReg ToExtReg(size_t base, bool bit) {
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return ExtReg::D0 + (base + (bit ? 16 : 0));
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return ExtReg::D0 + (base + (bit ? 16 : 0));
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}
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}
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bool ArmTranslatorVisitor::v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t size, size_t align, Reg m) {
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std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t size, size_t align) {
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size_t nelem, regs, inc;
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switch (type.ZeroExtend()) {
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switch (type.ZeroExtend()) {
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case 0b0111: // VLD1 A1
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case 0b0111: // VST1 A1 / VLD1 A1
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nelem = 1;
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regs = 1;
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inc = 0;
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if (Common::Bit<1>(align)) {
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if (Common::Bit<1>(align)) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{1, 1, 0};
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case 0b1010: // VLD1 A2
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case 0b1010: // VST1 A2 / VLD1 A2
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nelem = 1;
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regs = 2;
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inc = 0;
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if (align == 0b11) {
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if (align == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{1, 2, 0};
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case 0b0110: // VLD1 A3
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case 0b0110: // VST1 A3 / VLD1 A3
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nelem = 1;
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regs = 3;
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inc = 0;
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if (Common::Bit<1>(align)) {
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if (Common::Bit<1>(align)) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{1, 3, 0};
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case 0b0010: // VLD1 A4
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case 0b0010: // VST1 A4 / VLD1 A4
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nelem = 1;
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return std::tuple<size_t, size_t, size_t>{1, 4, 0};
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regs = 4;
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case 0b1000: // VST2 A1 / VLD2 A1
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inc = 0;
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break;
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case 0b1000: // VLD2 A1
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nelem = 2;
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regs = 1;
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inc = 1;
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if (size == 0b11 || align == 0b11) {
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if (size == 0b11 || align == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{2, 1, 1};
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case 0b1001: // VLD2 A1
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case 0b1001: // VST2 A1 / VLD2 A1
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nelem = 2;
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regs = 1;
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inc = 2;
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if (size == 0b11 || align == 0b11) {
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if (size == 0b11 || align == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{2, 1, 2};
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case 0b0011: // VLD2 A2
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case 0b0011: // VST2 A2 / VLD2 A2
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nelem = 2;
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regs = 2;
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inc = 2;
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if (size == 0b11) {
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if (size == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{2, 2, 2};
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case 0b0100: // VLD3
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case 0b0100: // VST3 / VLD3
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nelem = 3;
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regs = 1;
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inc = 1;
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if (size == 0b11 || Common::Bit<1>(align)) {
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if (size == 0b11 || Common::Bit<1>(align)) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{3, 1, 1};
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case 0b0101: // VLD3
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case 0b0101: // VST3 / VLD3
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nelem = 3;
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regs = 1;
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inc = 2;
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if (size == 0b11 || Common::Bit<1>(align)) {
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if (size == 0b11 || Common::Bit<1>(align)) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{3, 1, 2};
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case 0b0000: // VLD4
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case 0b0000: // VST4 / VLD4
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nelem = 4;
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regs = 1;
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inc = 1;
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if (size == 0b11) {
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if (size == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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}
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break;
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return std::tuple<size_t, size_t, size_t>{4, 1, 1};
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case 0b0001: // VLD4
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case 0b0001: // VST4 / VLD4
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nelem = 4;
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regs = 1;
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inc = 2;
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if (size == 0b11) {
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if (size == 0b11) {
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return UndefinedInstruction();
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return std::nullopt;
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}
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return std::tuple<size_t, size_t, size_t>{4, 1, 2};
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}
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}
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break;
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default:
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ASSERT_FALSE("Decode error");
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ASSERT_FALSE("Decode error");
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}
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} // anoynmous namespace
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bool ArmTranslatorVisitor::v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t size, size_t align, Reg m) {
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const auto decoded_type = DecodeType(type, size, align);
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if (!decoded_type) {
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return UndefinedInstruction();
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}
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const auto [nelem, regs, inc] = *decoded_type;
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const ExtReg d = ToExtReg(Vd, D);
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const size_t d_last = RegNumber(d) + inc * (nelem - 1);
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if (n == Reg::R15 || d_last + regs > 32) {
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return UnpredictableInstruction();
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}
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}
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const ExtReg d = ToExtRegD(Vd, D);
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[[maybe_unused]] const size_t alignment = align == 0 ? 1 : 4 << align;
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const size_t ebytes = static_cast<size_t>(1) << size;
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const size_t elements = 8 / ebytes;
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const bool wback = m != Reg::R15;
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const bool register_index = m != Reg::R15 && m != Reg::R13;
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IR::U32 address = ir.GetRegister(n);
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for (size_t r = 0; r < regs; r++) {
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for (size_t e = 0; e < elements; e++) {
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for (size_t i = 0; i < nelem; i++) {
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const ExtReg ext_reg = d + i * inc + r;
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const IR::U64 shifted_element = ir.LogicalShiftRight(ir.GetExtendedRegister(ext_reg), ir.Imm8(static_cast<u8>(e * ebytes * 8)));
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const IR::UAny element = ir.LeastSignificant(8 * ebytes, shifted_element);
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ir.WriteMemory(8 * ebytes, address, element);
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address = ir.Add(address, ir.Imm32(static_cast<u32>(ebytes)));
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}
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}
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}
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if (wback) {
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if (register_index) {
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ir.SetRegister(n, ir.Add(ir.GetRegister(n), ir.GetRegister(m)));
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} else {
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ir.SetRegister(n, ir.Add(ir.GetRegister(n), ir.Imm32(static_cast<u32>(8 * nelem * regs))));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t size, size_t align, Reg m) {
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const auto decoded_type = DecodeType(type, size, align);
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if (!decoded_type) {
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return UndefinedInstruction();
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}
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const auto [nelem, regs, inc] = *decoded_type;
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const ExtReg d = ToExtReg(Vd, D);
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const size_t d_last = RegNumber(d) + inc * (nelem - 1);
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const size_t d_last = RegNumber(d) + inc * (nelem - 1);
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if (n == Reg::R15 || d_last + regs > 32) {
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if (n == Reg::R15 || d_last + regs > 32) {
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return UnpredictableInstruction();
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return UnpredictableInstruction();
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@ -440,6 +440,7 @@ struct ArmTranslatorVisitor final {
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bool asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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// Advanced SIMD load/store structures
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// Advanced SIMD load/store structures
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bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);
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bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);
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bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);
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};
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};
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@ -41,14 +41,26 @@ U128 IREmitter::Pack2x64To1x128(const U64& lo, const U64& hi) {
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return Inst<U128>(Opcode::Pack2x64To1x128, lo, hi);
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return Inst<U128>(Opcode::Pack2x64To1x128, lo, hi);
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}
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}
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U32 IREmitter::LeastSignificantWord(const U64& value) {
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UAny IREmitter::LeastSignificant(size_t bitsize, const U32U64& value) {
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return Inst<U32>(Opcode::LeastSignificantWord, value);
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switch (bitsize) {
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case 8:
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return LeastSignificantByte(value);
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case 16:
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return LeastSignificantHalf(value);
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case 32:
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if (value.GetType() == Type::U32) {
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return value;
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}
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return LeastSignificantWord(value);
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case 64:
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ASSERT(value.GetType() == Type::U64);
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return value;
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}
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ASSERT_FALSE("Invalid bitsize");
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}
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}
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ResultAndCarry<U32> IREmitter::MostSignificantWord(const U64& value) {
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U32 IREmitter::LeastSignificantWord(const U64& value) {
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const auto result = Inst<U32>(Opcode::MostSignificantWord, value);
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return Inst<U32>(Opcode::LeastSignificantWord, value);
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const auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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}
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U16 IREmitter::LeastSignificantHalf(U32U64 value) {
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U16 IREmitter::LeastSignificantHalf(U32U64 value) {
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@ -65,6 +77,12 @@ U8 IREmitter::LeastSignificantByte(U32U64 value) {
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return Inst<U8>(Opcode::LeastSignificantByte, value);
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return Inst<U8>(Opcode::LeastSignificantByte, value);
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}
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}
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ResultAndCarry<U32> IREmitter::MostSignificantWord(const U64& value) {
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const auto result = Inst<U32>(Opcode::MostSignificantWord, value);
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const auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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U1 IREmitter::MostSignificantBit(const U32& value) {
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U1 IREmitter::MostSignificantBit(const U32& value) {
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return Inst<U1>(Opcode::MostSignificantBit, value);
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return Inst<U1>(Opcode::MostSignificantBit, value);
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}
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}
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@ -87,10 +87,11 @@ public:
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U64 Pack2x32To1x64(const U32& lo, const U32& hi);
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U64 Pack2x32To1x64(const U32& lo, const U32& hi);
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U128 Pack2x64To1x128(const U64& lo, const U64& hi);
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U128 Pack2x64To1x128(const U64& lo, const U64& hi);
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UAny LeastSignificant(size_t bitsize, const U32U64& value);
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U32 LeastSignificantWord(const U64& value);
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U32 LeastSignificantWord(const U64& value);
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ResultAndCarry<U32> MostSignificantWord(const U64& value);
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U16 LeastSignificantHalf(U32U64 value);
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U16 LeastSignificantHalf(U32U64 value);
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U8 LeastSignificantByte(U32U64 value);
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U8 LeastSignificantByte(U32U64 value);
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ResultAndCarry<U32> MostSignificantWord(const U64& value);
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U1 MostSignificantBit(const U32& value);
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U1 MostSignificantBit(const U32& value);
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U1 IsZero(const U32& value);
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U1 IsZero(const U32& value);
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U1 IsZero(const U64& value);
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U1 IsZero(const U64& value);
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@ -94,9 +94,9 @@ OPCODE(NZCVFromPackedFlags, NZCV, U32
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OPCODE(Pack2x32To1x64, U64, U32, U32 )
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OPCODE(Pack2x32To1x64, U64, U32, U32 )
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OPCODE(Pack2x64To1x128, U128, U64, U64 )
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OPCODE(Pack2x64To1x128, U128, U64, U64 )
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OPCODE(LeastSignificantWord, U32, U64 )
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OPCODE(LeastSignificantWord, U32, U64 )
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OPCODE(MostSignificantWord, U32, U64 )
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OPCODE(LeastSignificantHalf, U16, U32 )
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OPCODE(LeastSignificantHalf, U16, U32 )
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OPCODE(LeastSignificantByte, U8, U32 )
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OPCODE(LeastSignificantByte, U8, U32 )
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OPCODE(MostSignificantWord, U32, U64 )
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OPCODE(MostSignificantBit, U1, U32 )
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OPCODE(MostSignificantBit, U1, U32 )
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OPCODE(IsZero32, U1, U32 )
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OPCODE(IsZero32, U1, U32 )
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OPCODE(IsZero64, U1, U64 )
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OPCODE(IsZero64, U1, U64 )
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