diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index f630bb98..64980928 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -675,7 +675,7 @@ INST(DUP_gen, "DUP (general)", "0Q001 INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd") INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd") //INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd") -//INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd") +INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd") // Data Processing - FP and SIMD - SIMD Three same //INST(FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_copy.cpp b/src/frontend/A64/translate/impl/simd_copy.cpp index 415e6861..816f9d61 100644 --- a/src/frontend/A64/translate/impl/simd_copy.cpp +++ b/src/frontend/A64/translate/impl/simd_copy.cpp @@ -73,4 +73,21 @@ bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { return true; } +bool TranslatorVisitor::INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) { + const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + if (size > 3) return UnallocatedEncoding(); + + const size_t dst_index = imm5.ZeroExtend() >> (size + 1); + const size_t src_index = imm4.ZeroExtend() >> size; + const size_t idxdsize = imm4.Bit<3>() ? 128 : 64; + const size_t esize = 8 << size; + + const IR::U128 operand = V(idxdsize, Vn); + const IR::UAny elem = ir.VectorGetElement(esize, operand, src_index); + const IR::U128 result = ir.VectorSetElement(esize, V(128, Vd), dst_index, elem); + V(128, Vd, result); + + return true; +} + } // namespace Dynarmic::A64