From d4b05b28cfeae3e03918dcd6626a5ef7446d44ce Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 23 Jan 2018 18:22:42 +0000 Subject: [PATCH] A64: Implement CLS This is not the cleanest implementation. --- src/frontend/A64/decoder/a64.inc | 2 +- .../A64/translate/impl/data_processing_register.cpp | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index c10ff66e..c540209f 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -289,7 +289,7 @@ INST(RORV, "RORV", "z0011 INST(REV16_int, "REV16", "z101101011000000000001nnnnnddddd") INST(REV, "REV", "z10110101100000000001onnnnnddddd") INST(CLZ_int, "CLZ", "z101101011000000000100nnnnnddddd") -//INST(CLS_int, "CLS", "z101101011000000000101nnnnnddddd") +INST(CLS_int, "CLS", "z101101011000000000101nnnnnddddd") INST(REV32_int, "REV32", "1101101011000000000010nnnnnddddd") //INST(PACDA, "PACDA, PACDZA", "110110101100000100Z010nnnnnddddd") //INST(PACDB, "PACDB, PACDZB", "110110101100000100Z011nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/data_processing_register.cpp b/src/frontend/A64/translate/impl/data_processing_register.cpp index f775cd8d..e3afcb61 100644 --- a/src/frontend/A64/translate/impl/data_processing_register.cpp +++ b/src/frontend/A64/translate/impl/data_processing_register.cpp @@ -19,6 +19,16 @@ bool TranslatorVisitor::CLZ_int(bool sf, Reg Rn, Reg Rd) { return true; } +bool TranslatorVisitor::CLS_int(bool sf, Reg Rn, Reg Rd) { + const size_t datasize = sf ? 64 : 32; + + const IR::U32U64 operand = X(datasize, Rn); + const IR::U32U64 result = ir.Sub(ir.CountLeadingZeros(ir.Eor(operand, ir.ArithmeticShiftRight(operand, ir.Imm8(u8(datasize))))), I(datasize, 1)); + + X(datasize, Rd, result); + return true; +} + bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd) { const size_t datasize = sf ? 64 : 32;