branch: Make variables const where applicable
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parent
867b666285
commit
da55ed7b31
1 changed files with 37 additions and 37 deletions
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@ -9,36 +9,36 @@
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namespace Dynarmic::A64 {
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
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bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
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s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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const u64 target = ir.PC() + offset;
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u64 target = ir.PC() + offset;
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const auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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const auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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ir.SetTerm(IR::Term::If{cond, cond_pass, cond_fail});
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ir.SetTerm(IR::Term::If{cond, cond_pass, cond_fail});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::B_uncond(Imm<26> imm26) {
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bool TranslatorVisitor::B_uncond(Imm<26> imm26) {
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s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
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const u64 target = ir.PC() + offset;
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u64 target = ir.PC() + offset;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::BL(Imm<26> imm26) {
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bool TranslatorVisitor::BL(Imm<26> imm26) {
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s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
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X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
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X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
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ir.PushRSB(ir.current_location->AdvancePC(4));
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ir.PushRSB(ir.current_location->AdvancePC(4));
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u64 target = ir.PC() + offset;
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const u64 target = ir.PC() + offset;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::BLR(Reg Rn) {
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bool TranslatorVisitor::BLR(Reg Rn) {
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auto target = X(64, Rn);
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const auto target = X(64, Rn);
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X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
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X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
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ir.PushRSB(ir.current_location->AdvancePC(4));
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ir.PushRSB(ir.current_location->AdvancePC(4));
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@ -49,7 +49,7 @@ bool TranslatorVisitor::BLR(Reg Rn) {
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}
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}
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bool TranslatorVisitor::BR(Reg Rn) {
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bool TranslatorVisitor::BR(Reg Rn) {
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auto target = X(64, Rn);
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const auto target = X(64, Rn);
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ir.SetPC(target);
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ir.SetPC(target);
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ir.SetTerm(IR::Term::FastDispatchHint{});
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ir.SetTerm(IR::Term::FastDispatchHint{});
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@ -57,7 +57,7 @@ bool TranslatorVisitor::BR(Reg Rn) {
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}
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}
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bool TranslatorVisitor::RET(Reg Rn) {
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bool TranslatorVisitor::RET(Reg Rn) {
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auto target = X(64, Rn);
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const auto target = X(64, Rn);
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ir.SetPC(target);
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ir.SetPC(target);
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ir.SetTerm(IR::Term::PopRSBHint{});
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ir.SetTerm(IR::Term::PopRSBHint{});
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@ -65,63 +65,63 @@ bool TranslatorVisitor::RET(Reg Rn) {
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}
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}
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bool TranslatorVisitor::CBZ(bool sf, Imm<19> imm19, Reg Rt) {
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bool TranslatorVisitor::CBZ(bool sf, Imm<19> imm19, Reg Rt) {
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size_t datasize = sf ? 64 : 32;
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const size_t datasize = sf ? 64 : 32;
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s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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IR::U32U64 operand1 = X(datasize, Rt);
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const IR::U32U64 operand1 = X(datasize, Rt);
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ir.SetCheckBit(ir.IsZero(operand1));
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ir.SetCheckBit(ir.IsZero(operand1));
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u64 target = ir.PC() + offset;
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const u64 target = ir.PC() + offset;
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auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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const auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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const auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
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ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
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bool TranslatorVisitor::CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
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size_t datasize = sf ? 64 : 32;
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const size_t datasize = sf ? 64 : 32;
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s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
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IR::U32U64 operand1 = X(datasize, Rt);
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const IR::U32U64 operand1 = X(datasize, Rt);
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ir.SetCheckBit(ir.IsZero(operand1));
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ir.SetCheckBit(ir.IsZero(operand1));
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u64 target = ir.PC() + offset;
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const u64 target = ir.PC() + offset;
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auto cond_pass = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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const auto cond_pass = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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auto cond_fail = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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const auto cond_fail = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
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ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
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bool TranslatorVisitor::TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
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size_t datasize = b5 == 1 ? 64 : 32;
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const size_t datasize = b5 == 1 ? 64 : 32;
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u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
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const u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
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s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
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auto operand = X(datasize, Rt);
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const auto operand = X(datasize, Rt);
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ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
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ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
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u64 target = ir.PC() + offset;
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const u64 target = ir.PC() + offset;
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auto cond_1 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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const auto cond_1 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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auto cond_0 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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const auto cond_0 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
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ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
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return false;
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return false;
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}
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}
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bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
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bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
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size_t datasize = b5 == 1 ? 64 : 32;
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const size_t datasize = b5 == 1 ? 64 : 32;
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u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
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const u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
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s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
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const s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
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auto operand = X(datasize, Rt);
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const auto operand = X(datasize, Rt);
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ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
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ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
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u64 target = ir.PC() + offset;
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const u64 target = ir.PC() + offset;
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auto cond_1 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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const auto cond_1 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
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auto cond_0 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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const auto cond_0 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
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ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
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ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
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return false;
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return false;
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}
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}
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