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branch: Make variables const where applicable

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Lioncash 2018-09-17 21:28:43 -04:00 committed by MerryMage
parent 867b666285
commit da55ed7b31
1 changed files with 37 additions and 37 deletions
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74
src/frontend/A64/translate/impl/branch.cpp
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@ -9,36 +9,36 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) { bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
const u64 target = ir.PC() + offset;
u64 target = ir.PC() + offset; const auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)}; const auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::If{cond, cond_pass, cond_fail}); ir.SetTerm(IR::Term::If{cond, cond_pass, cond_fail});
return false; return false;
} }
bool TranslatorVisitor::B_uncond(Imm<26> imm26) { bool TranslatorVisitor::B_uncond(Imm<26> imm26) {
s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
const u64 target = ir.PC() + offset;
u64 target = ir.PC() + offset;
ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)}); ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
return false; return false;
} }
bool TranslatorVisitor::BL(Imm<26> imm26) { bool TranslatorVisitor::BL(Imm<26> imm26) {
s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
X(64, Reg::R30, ir.Imm64(ir.PC() + 4)); X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
ir.PushRSB(ir.current_location->AdvancePC(4)); ir.PushRSB(ir.current_location->AdvancePC(4));
u64 target = ir.PC() + offset; const u64 target = ir.PC() + offset;
ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)}); ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
return false; return false;
} }
bool TranslatorVisitor::BLR(Reg Rn) { bool TranslatorVisitor::BLR(Reg Rn) {
auto target = X(64, Rn); const auto target = X(64, Rn);
X(64, Reg::R30, ir.Imm64(ir.PC() + 4)); X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
ir.PushRSB(ir.current_location->AdvancePC(4)); ir.PushRSB(ir.current_location->AdvancePC(4));
@ -49,7 +49,7 @@ bool TranslatorVisitor::BLR(Reg Rn) {
} }
bool TranslatorVisitor::BR(Reg Rn) { bool TranslatorVisitor::BR(Reg Rn) {
auto target = X(64, Rn); const auto target = X(64, Rn);
ir.SetPC(target); ir.SetPC(target);
ir.SetTerm(IR::Term::FastDispatchHint{}); ir.SetTerm(IR::Term::FastDispatchHint{});
@ -57,7 +57,7 @@ bool TranslatorVisitor::BR(Reg Rn) {
} }
bool TranslatorVisitor::RET(Reg Rn) { bool TranslatorVisitor::RET(Reg Rn) {
auto target = X(64, Rn); const auto target = X(64, Rn);
ir.SetPC(target); ir.SetPC(target);
ir.SetTerm(IR::Term::PopRSBHint{}); ir.SetTerm(IR::Term::PopRSBHint{});
@ -65,63 +65,63 @@ bool TranslatorVisitor::RET(Reg Rn) {
} }
bool TranslatorVisitor::CBZ(bool sf, Imm<19> imm19, Reg Rt) { bool TranslatorVisitor::CBZ(bool sf, Imm<19> imm19, Reg Rt) {
size_t datasize = sf ? 64 : 32; const size_t datasize = sf ? 64 : 32;
s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
IR::U32U64 operand1 = X(datasize, Rt); const IR::U32U64 operand1 = X(datasize, Rt);
ir.SetCheckBit(ir.IsZero(operand1)); ir.SetCheckBit(ir.IsZero(operand1));
u64 target = ir.PC() + offset; const u64 target = ir.PC() + offset;
auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)}; const auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)}; const auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail}); ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
return false; return false;
} }
bool TranslatorVisitor::CBNZ(bool sf, Imm<19> imm19, Reg Rt) { bool TranslatorVisitor::CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
size_t datasize = sf ? 64 : 32; const size_t datasize = sf ? 64 : 32;
s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
IR::U32U64 operand1 = X(datasize, Rt); const IR::U32U64 operand1 = X(datasize, Rt);
ir.SetCheckBit(ir.IsZero(operand1)); ir.SetCheckBit(ir.IsZero(operand1));
u64 target = ir.PC() + offset; const u64 target = ir.PC() + offset;
auto cond_pass = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)}; const auto cond_pass = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->SetPC(target)}; const auto cond_fail = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail}); ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
return false; return false;
} }
bool TranslatorVisitor::TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) { bool TranslatorVisitor::TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
size_t datasize = b5 == 1 ? 64 : 32; const size_t datasize = b5 == 1 ? 64 : 32;
u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>(); const u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
auto operand = X(datasize, Rt); const auto operand = X(datasize, Rt);
ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos))); ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
u64 target = ir.PC() + offset; const u64 target = ir.PC() + offset;
auto cond_1 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)}; const auto cond_1 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location->SetPC(target)}; const auto cond_0 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0}); ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
return false; return false;
} }
bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) { bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
size_t datasize = b5 == 1 ? 64 : 32; const size_t datasize = b5 == 1 ? 64 : 32;
u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>(); const u8 bit_pos = concatenate(b5, b40).ZeroExtend<u8>();
s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>(); const s64 offset = concatenate(imm14, Imm<2>{0}).SignExtend<s64>();
auto operand = X(datasize, Rt); const auto operand = X(datasize, Rt);
ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos))); ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
u64 target = ir.PC() + offset; const u64 target = ir.PC() + offset;
auto cond_1 = IR::Term::LinkBlock{ir.current_location->SetPC(target)}; const auto cond_1 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)}; const auto cond_0 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0}); ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
return false; return false;
} }