From db24e1f09b9058605930c48800b086e7cf5ddc74 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 5 Sep 2018 15:59:51 -0400 Subject: [PATCH] A64: Implement SQABS' scalar variant --- src/frontend/A64/decoder/a64.inc | 2 +- .../translate/impl/simd_scalar_two_register_misc.cpp | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 9b981867..8dd34637 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -407,7 +407,7 @@ INST(FRSQRTE_2, "FRSQRTE", "01111 // Data Processing - FP and SIMD - Scalar two-register misc //INST(SUQADD_1, "SUQADD", "01011110zz100000001110nnnnnddddd") -//INST(SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd") +INST(SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd") INST(CMGT_zero_1, "CMGT (zero)", "01011110zz100000100010nnnnnddddd") INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd") INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index e5890b2a..c90d6b99 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -205,6 +205,16 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SQABS_1(Imm<2> size, Vec Vn, Vec Vd) { + const size_t esize = 8 << size.ZeroExtend(); + + const IR::U128 operand = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0)); + const IR::U128 result = ir.VectorSignedSaturatedAbs(esize, operand); + + V(128, Vd, result); + return true; +} + bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) { return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned); }