From e1a266b9299be81cc0318c7e25b00388c342704f Mon Sep 17 00:00:00 2001 From: merry Date: Sun, 20 Mar 2022 09:38:11 +0000 Subject: [PATCH] A32: Implement SHA256SU1 --- src/dynarmic/frontend/A32/decoder/asimd.inc | 1 + .../A32/translate/impl/a32_translate_impl.h | 1 + .../A32/translate/impl/asimd_three_regs.cpp | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/src/dynarmic/frontend/A32/decoder/asimd.inc b/src/dynarmic/frontend/A32/decoder/asimd.inc index d943b22c..743c4fd5 100644 --- a/src/dynarmic/frontend/A32/decoder/asimd.inc +++ b/src/dynarmic/frontend/A32/decoder/asimd.inc @@ -52,6 +52,7 @@ INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd111 INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD INST(v8_SHA256H, "SHA256H", "111100110D00nnnndddd1100NQM0mmmm") // v8 INST(v8_SHA256H2, "SHA256H2", "111100110D01nnnndddd1100NQM0mmmm") // v8 +INST(v8_SHA256SU1, "SHA256SU1", "111100110D10nnnndddd1100NQM0mmmm") // v8 // Three registers of different lengths INST(asimd_VADDL, "VADDL/VADDW", "1111001U1Dzznnnndddd000oN0M0mmmm") // ASIMD diff --git a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h index f588a003..c7ef1b6e 100644 --- a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h +++ b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h @@ -877,6 +877,7 @@ struct TranslatorVisitor final { bool asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool v8_SHA256H(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool v8_SHA256SU1(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); // Advanced SIMD three registers with different lengths bool asimd_VADDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm); diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp index a1b5cf4d..f803d059 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp @@ -867,6 +867,24 @@ bool TranslatorVisitor::v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q return true; } +bool TranslatorVisitor::v8_SHA256SU1(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + if (!Q || Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto n = ToVector(Q, Vn, N); + const auto m = ToVector(Q, Vm, M); + + const auto x = ir.GetVector(d); + const auto y = ir.GetVector(n); + const auto z = ir.GetVector(m); + const auto result = ir.SHA256MessageSchedule1(x, y, z); + + ir.SetVector(d, result); + return true; +} + // ASIMD Three registers of different length bool TranslatorVisitor::asimd_VADDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm) {