MerryMage
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8ff414ee0e
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Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
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2016-08-06 20:03:15 +01:00 |
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bunnei
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2448d52394
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load_store: Use correct types for LDR/STR.
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2016-08-05 20:51:32 -04:00 |
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bunnei
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8c2300d477
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arm: Implement LDRD reg/imm instructions.
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2016-08-05 20:05:02 -04:00 |
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bunnei
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ec3a98cf95
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arm: Implement LDRH reg/imm instructions.
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2016-08-05 20:05:01 -04:00 |
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bunnei
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192a0fba7a
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arm: Implement LDRB reg/imm instructions.
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2016-08-05 20:05:00 -04:00 |
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bunnei
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dfb318f208
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arm: Implement STRD reg/imm instructions.
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2016-08-05 20:04:59 -04:00 |
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bunnei
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e931dc2496
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arm: Implement STRH reg/imm instructions.
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2016-08-05 20:04:58 -04:00 |
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bunnei
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9f77662b24
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arm: Implement STRB reg/imm instructions.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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caab1bbc7c
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arm: Implement STR reg/imm instructions.
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2016-08-05 20:04:56 -04:00 |
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bunnei
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b09ecb4532
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arm: Implement LDR reg/imm instructions.
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2016-08-05 20:04:55 -04:00 |
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Tillmann Karras
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fce8c86c90
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Implement RSB
somehow missed this earlier
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2016-08-05 02:13:26 +01:00 |
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Tillmann Karras
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eb2e6e8bea
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Implement some multiplies
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2016-08-05 02:09:54 +01:00 |
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bunnei
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691e4139fa
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arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
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30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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a875c0c720
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TranslateArm: Stub more ARM instructions
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2016-08-02 21:59:33 +01:00 |
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MerryMage
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6097a21955
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TranslateArm: Reorganisation - Split visitor into multiple .cpp files
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2016-08-02 11:54:04 +01:00 |
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