MerryMage
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0e5593ba62
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TranslateArm: Implement SETEND
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2016-08-11 17:15:33 +01:00 |
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MerryMage
|
b4c586d5ef
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TranslateArm: VSTR: Correct behaviour in big-endian mode
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2016-08-10 16:43:37 +01:00 |
|
bunnei
|
8e8db6e137
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TranslateArm: Implement VSTR.
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2016-08-10 15:01:23 +01:00 |
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MerryMage
|
df39308e03
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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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MerryMage
|
d0d51ba346
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TranslateArm: Implement STM, STMDA, STMDB, STMIB
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2016-08-08 22:49:11 +01:00 |
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MerryMage
|
85549d7ae2
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TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
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2016-08-08 22:26:06 +01:00 |
|
MerryMage
|
edb236ab07
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Correct implementation of thumb16_SVC and arm_SVC
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2016-08-07 22:19:39 +01:00 |
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MerryMage
|
4dcd1d1859
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Arm: BLX is UNPREDICTABLE when Rm is PC
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2016-08-07 20:50:33 +01:00 |
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MerryMage
|
1af5bef32c
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TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
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2016-08-07 20:40:31 +01:00 |
|
MerryMage
|
939bb5c0cb
|
TranslateArm: Implement NOP
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2016-08-07 20:08:31 +01:00 |
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MerryMage
|
e48df9d8fd
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TranslateArm: Implement Hint instructions as NOPs
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2016-08-07 20:04:48 +01:00 |
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MerryMage
|
3a465ba4a8
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VFP: Implement VLDR
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2016-08-07 19:59:35 +01:00 |
|
MerryMage
|
a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
|
MerryMage
|
0f412247ed
|
VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
|
MerryMage
|
cd8e7c0504
|
VFP: Implement VNEG
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2016-08-07 12:04:21 +01:00 |
|
MerryMage
|
da33af5abe
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VFP: Implement VMLA, VMLS, VNMLA, VNMLS
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2016-08-07 11:49:06 +01:00 |
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MerryMage
|
3f1345a1a5
|
VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
|
MerryMage
|
12e7f2c359
|
VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
|
MerryMage
|
97b5fa173f
|
VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
|
MerryMage
|
ce6b5f8210
|
VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
|
MerryMage
|
c35f06470f
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VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
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2016-08-06 23:01:18 +01:00 |
|
Tillmann Karras
|
55204a80d0
|
Implement SMMLA, SMMLS, SMMUL
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2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
|
b9f4f1ed0f
|
Add carry support to MostSignificantWord
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2016-08-06 21:17:11 +01:00 |
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MerryMage
|
7915f97d98
|
TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
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2016-08-06 20:42:06 +01:00 |
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MerryMage
|
4b31ea25a7
|
VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
8ff414ee0e
|
Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
|
2016-08-06 20:03:15 +01:00 |
|
bunnei
|
2448d52394
|
load_store: Use correct types for LDR/STR.
|
2016-08-05 20:51:32 -04:00 |
|
bunnei
|
8c2300d477
|
arm: Implement LDRD reg/imm instructions.
|
2016-08-05 20:05:02 -04:00 |
|
bunnei
|
ec3a98cf95
|
arm: Implement LDRH reg/imm instructions.
|
2016-08-05 20:05:01 -04:00 |
|
bunnei
|
192a0fba7a
|
arm: Implement LDRB reg/imm instructions.
|
2016-08-05 20:05:00 -04:00 |
|
bunnei
|
dfb318f208
|
arm: Implement STRD reg/imm instructions.
|
2016-08-05 20:04:59 -04:00 |
|
bunnei
|
e931dc2496
|
arm: Implement STRH reg/imm instructions.
|
2016-08-05 20:04:58 -04:00 |
|
bunnei
|
9f77662b24
|
arm: Implement STRB reg/imm instructions.
|
2016-08-05 20:04:57 -04:00 |
|
bunnei
|
caab1bbc7c
|
arm: Implement STR reg/imm instructions.
|
2016-08-05 20:04:56 -04:00 |
|
bunnei
|
b09ecb4532
|
arm: Implement LDR reg/imm instructions.
|
2016-08-05 20:04:55 -04:00 |
|
Tillmann Karras
|
fce8c86c90
|
Implement RSB
somehow missed this earlier
|
2016-08-05 02:13:26 +01:00 |
|
Tillmann Karras
|
eb2e6e8bea
|
Implement some multiplies
|
2016-08-05 02:09:54 +01:00 |
|
bunnei
|
691e4139fa
|
arm: Implement B/BL/BX instructions.
|
2016-08-03 16:49:01 -04:00 |
|
Tillmann Karras
|
fc33f1d374
|
Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
|
2016-08-03 00:47:17 +01:00 |
|
Tillmann Karras
|
30a90295b9
|
Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
|
2016-08-03 00:47:16 +01:00 |
|
MerryMage
|
a875c0c720
|
TranslateArm: Stub more ARM instructions
|
2016-08-02 21:59:33 +01:00 |
|
MerryMage
|
6097a21955
|
TranslateArm: Reorganisation - Split visitor into multiple .cpp files
|
2016-08-02 11:54:04 +01:00 |
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