MerryMage
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6c45619aa1
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Optimization: Implement terminal LinkBlockFast
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2016-08-15 14:33:17 +01:00 |
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MerryMage
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624e84fa09
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Optimization: Tweak RSB
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2016-08-15 14:08:06 +01:00 |
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MerryMage
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070298b948
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Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect
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2016-08-15 13:21:58 +01:00 |
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MerryMage
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e164ede4dc
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TranslateArm: Implement MRS, MSR (imm), MSR (reg)
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2016-08-15 11:50:49 +01:00 |
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bunnei
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30f3d869cc
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TranslateArm: Implement VPUSH and VPOP.
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2016-08-13 19:37:03 +01:00 |
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MerryMage
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9c82a12f8f
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ir_opt: Update VerificationPass to current IR
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2016-08-13 18:39:49 +01:00 |
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MerryMage
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8fc21f481a
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RegAlloc: Handle case when def is unused
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2016-08-13 01:55:03 +01:00 |
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MerryMage
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d43d97b990
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EmitX64/EmitPushRSB: Assert that patch location is of correct size
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2016-08-13 00:52:31 +01:00 |
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MerryMage
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960d14d18e
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Optimization: Implement Return Stack Buffer
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2016-08-13 00:10:23 +01:00 |
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bunnei
|
8e68e6fdd9
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TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
4b09c0d032
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TranslateArm: Implement QADD8 and UQADD8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
127fbe99cb
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TranslateArm: Implement QSUB8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
86fe29c6d2
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TranslateArm: Implement UQSUB8.
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2016-08-12 19:00:44 +01:00 |
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MerryMage
|
1029fd27ce
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Update documentation (2016-08-12)
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2016-08-12 18:17:31 +01:00 |
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MerryMage
|
3808938c98
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Fix SETEND
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2016-08-11 19:15:58 +01:00 |
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bunnei
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218980cf69
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load_store: Implement LDRSB and LDRSH.
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2016-08-11 17:18:20 +01:00 |
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MerryMage
|
0e5593ba62
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TranslateArm: Implement SETEND
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2016-08-11 17:15:33 +01:00 |
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MerryMage
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8964b38cf9
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IR/DumpBlock: Print references to ExtRegs
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2016-08-11 17:15:02 +01:00 |
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MerryMage
|
b4c586d5ef
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TranslateArm: VSTR: Correct behaviour in big-endian mode
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2016-08-10 16:43:37 +01:00 |
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MerryMage
|
945498a16a
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DisassemblerArm: Disassemble SETEND
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2016-08-10 16:15:07 +01:00 |
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bunnei
|
8e8db6e137
|
TranslateArm: Implement VSTR.
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2016-08-10 15:01:23 +01:00 |
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MerryMage
|
df39308e03
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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MerryMage
|
d921390928
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TranslateArm: Add santity check to see if we've emitted a terminal instruction
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2016-08-09 22:47:41 +01:00 |
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MerryMage
|
2eec43178a
|
IR: Opaque can be of any type
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2016-08-09 22:46:44 +01:00 |
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MerryMage
|
29d30bf931
|
Interface: Added Jit::Reset to reset CPU state
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2016-08-09 22:45:54 +01:00 |
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MerryMage
|
82f42d065f
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DisassemblerArm: Implemented disassembly of STR*/LDR* instructions
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2016-08-09 22:44:42 +01:00 |
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MerryMage
|
d0d51ba346
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TranslateArm: Implement STM, STMDA, STMDB, STMIB
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2016-08-08 22:49:11 +01:00 |
|
Tillmann Karras
|
5d26899ac9
|
Add simplified LogicalShiftRight64 IR opcode
|
2016-08-08 22:27:05 +01:00 |
|
Tillmann Karras
|
ccb2aa96a5
|
Add support for the APSR.Q flag
|
2016-08-08 22:27:04 +01:00 |
|
Tillmann Karras
|
11e0688e5f
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Fix build on case-sensitive file systems
|
2016-08-08 22:27:03 +01:00 |
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MerryMage
|
85549d7ae2
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TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
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2016-08-08 22:26:06 +01:00 |
|
MerryMage
|
46e4864707
|
ArmTypes: Add RegListToString and reorganise
|
2016-08-08 22:20:28 +01:00 |
|
MerryMage
|
975f011fc0
|
BackendX64/RegAlloc: Do not allocate RSP for guest use
|
2016-08-08 16:01:07 +01:00 |
|
MerryMage
|
abd113f160
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EmitX64: Renamed patch_jmp_locations to patch_jg_locations
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2016-08-08 15:56:07 +01:00 |
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MerryMage
|
52fa998e6b
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EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags
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2016-08-07 22:47:43 +01:00 |
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MerryMage
|
04c1a0d2de
|
EmitX64: Switch MXCSR when switching to interpreter
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2016-08-07 22:47:17 +01:00 |
|
MerryMage
|
edb236ab07
|
Correct implementation of thumb16_SVC and arm_SVC
|
2016-08-07 22:19:39 +01:00 |
|
MerryMage
|
a32063fa60
|
EmitX64: Implement block linking
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2016-08-07 22:11:39 +01:00 |
|
MerryMage
|
b3bb1d5048
|
Tests: Tidy up ARM fuzz tests
|
2016-08-07 21:55:38 +01:00 |
|
MerryMage
|
328422b740
|
RegAlloc: HostCall flushes all XMM regsiters
|
2016-08-07 21:02:16 +01:00 |
|
MerryMage
|
4dcd1d1859
|
Arm: BLX is UNPREDICTABLE when Rm is PC
|
2016-08-07 20:50:33 +01:00 |
|
MerryMage
|
1af5bef32c
|
TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
|
2016-08-07 20:40:31 +01:00 |
|
MerryMage
|
939bb5c0cb
|
TranslateArm: Implement NOP
|
2016-08-07 20:08:31 +01:00 |
|
MerryMage
|
e48df9d8fd
|
TranslateArm: Implement Hint instructions as NOPs
|
2016-08-07 20:04:48 +01:00 |
|
MerryMage
|
3a465ba4a8
|
VFP: Implement VLDR
|
2016-08-07 19:59:35 +01:00 |
|
MerryMage
|
a2c2db277b
|
VFP: Implement VMOV (all variants)
|
2016-08-07 19:25:12 +01:00 |
|
MerryMage
|
aba705f6b9
|
BackendX64: Merge Routines into BlockOfCode
|
2016-08-07 18:08:48 +01:00 |
|
MerryMage
|
0f412247ed
|
VFP: Implement VSQRT
|
2016-08-07 12:19:07 +01:00 |
|
MerryMage
|
cd8e7c0504
|
VFP: Implement VNEG
|
2016-08-07 12:04:21 +01:00 |
|
MerryMage
|
da33af5abe
|
VFP: Implement VMLA, VMLS, VNMLA, VNMLS
|
2016-08-07 11:49:06 +01:00 |
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