MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2a6619d59c
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A64: Implement CLREX
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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Lioncash
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a9153218bd
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A64: Implement NOT (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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aed4fd3ec3
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A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5f77ab28ee
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A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3738043e58
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A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ce7628b6b5
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f1cb5581c9
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A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c9b4f0114
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A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1dd2b33b87
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A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5eac3abf52
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A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3afd2fcbad
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A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e7041d7196
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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faeb77e8c4
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A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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653c82d8f0
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impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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3f93c77ace
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A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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4e33629b0e
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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586854117b
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Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8ab7d8175c
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impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ea69cb4474
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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eb5591859c
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A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cc9efd13c9
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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2ee39d6b36
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A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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5a65313236
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab4664de61
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A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
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