Commit graph

922 commits

Author SHA1 Message Date
Lioncash
6177c2c63d CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a A64: Implement EOR3 and BCAX 2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2 impl: Update PC when raising exception 2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad A64: Implement FDIV (vector) 2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d Correct FPSR and FPCR 2020-04-22 20:46:15 +01:00
MerryMage
147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant 2020-04-22 20:46:15 +01:00
MerryMage
be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b A64: Implement NEG (vector) 2020-04-22 20:46:15 +01:00
MerryMage
710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage
2721bb5ace emit_x64_floating_point: Add maybe_unused to preprocess parameter 2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b A64: Implement FMINNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07 A64: Implement FMAXNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1dfce0894d constant_pool: Add frame parameter 2020-04-22 20:46:14 +01:00
MerryMage
bd2b415850 A64: Implement ADDP (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
84f1c9b7f4 reg_alloc: Only exchange GPRs 2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0 A64: Implement DUP (element), scalar variant 2020-04-22 20:46:14 +01:00
MerryMage
6541ec064d emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
7c193485e1 a64/config: Allow NaN emulation accuracy to be set 2020-04-22 20:46:14 +01:00
MerryMage
a3df46a75a a64_emit_x64: Add conf to A64EmitContext 2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198 A64: Implement FSQRT (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
07520f32c3 backend_x64: Accurately handle NaNs 2020-04-22 20:46:14 +01:00
MerryMage
e97581d063 fuzz_with_unicorn: Print AArch64 disassembly 2020-04-22 20:46:14 +01:00
MerryMage
01c1e9017e T32: Add initial decoder list 2020-04-22 20:46:14 +01:00
MerryMage
ccf7df057b simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) 2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab decoder/a64: Rearrange SIMD two-register misc decoders 2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06 A64: Implement CMGE (register) 2020-04-22 20:46:14 +01:00
MerryMage
9d85991906 A64: Implement CMHI, CMHS 2020-04-22 20:46:14 +01:00
MerryMage
e2b9b7c5b0 IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73 A64: Implement SMAX, SMIN, UMAX, UMIN 2020-04-22 20:46:14 +01:00
MerryMage
47c0ad0fc8 IR: Implement Vector{Max,Min}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f A64: Implement CMGT (register) 2020-04-22 20:46:14 +01:00
MerryMage
f4775910f5 IR: Implement VectorGreaterSigned 2020-04-22 20:46:14 +01:00
MerryMage
1f5b3bca43 Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
2020-04-22 20:46:14 +01:00
MerryMage
f3fa4a042f a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning) 2020-04-22 20:46:14 +01:00
MerryMage
8698f057d0 A64: Implement STXP, STLXP, LDXP, LDAXP 2020-04-22 20:46:14 +01:00
MerryMage
2a6619d59c A64: Implement CLREX 2020-04-22 20:46:14 +01:00
MerryMage
b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage
a6cc667509 Direct Page Table Access: Handle address spaces less than the full 64-bit in size 2020-04-22 20:46:14 +01:00
MerryMage
f45a5e17c6 Implement direct page table access 2020-04-22 20:46:14 +01:00
MerryMage
bfd3e30c75 callbacks: Member functions should be const 2020-04-22 20:46:14 +01:00
MerryMage
9f2f08db8d a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call 2020-04-22 20:46:14 +01:00
MerryMage
6c4773e85b abi: Add RAX to ABI_ALL_CALLER_SAVE 2020-04-22 20:46:14 +01:00
MerryMage
8756487554 A64: Partially implement MRS 2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
Lioncash
a9153218bd A64: Implement NOT (vector) 2020-04-22 20:46:14 +01:00
MerryMage
2cb0a699ba IR: Implement FPMax, FPMin 2020-04-22 20:46:14 +01:00
MerryMage
aed4fd3ec3 A64: Implement FADD (vector), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
98c8e7d1af IR: Implement FPVectorAdd 2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee A64: Implement SSHLL, SSHLL2 2020-04-22 20:46:14 +01:00
MerryMage
eae518a338 IR: Implement VectorSignExtend 2020-04-22 20:46:14 +01:00
MerryMage
3738043e58 A64: Implement DUP (element), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
ce7628b6b5 load_store_multiple_structures: Improve IR codegen for selem == 1 case 2020-04-22 20:46:14 +01:00
MerryMage
f1cb5581c9 A64: Implement FSUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b9cd345ddc IR: Implement FPVectorSub 2020-04-22 20:46:14 +01:00
MerryMage
851fc83445 emit_x64_vector: EmitOneArgumentFallback 2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b Forward declare IR::Opcode and IR::Type where possible 2020-04-22 20:46:14 +01:00
MerryMage
6c9b4f0114 A64: Implement CNT 2020-04-22 20:46:14 +01:00
MerryMage
303088a51e IR: Implement VectorPopulationCount 2020-04-22 20:46:14 +01:00
MerryMage
1dd2b33b87 A64: Implement MLS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
5eac3abf52 A64: Implement MLA (vector) 2020-04-22 20:46:14 +01:00
MerryMage
bf2cd92da9 emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64 2020-04-22 20:46:14 +01:00
MerryMage
b062266b8e emit_x64_vector: More explicit lambda decay 2020-04-22 20:46:14 +01:00
MerryMage
3afd2fcbad A64: Implement MUL (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b6de612e01 IR: Implement VectorMultiply 2020-04-22 20:46:14 +01:00
MerryMage
90a053a5e4 emit_x64_vector: Order alphabetically 2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) 2020-04-22 20:46:14 +01:00
MerryMage
a455ff70c9 decoder/a64: Don't rearrange unrelated decoders 2020-04-22 20:46:14 +01:00
MerryMage
faeb77e8c4 A64: Implement SUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage
bd106c3ae7 A64: Implement SIMD instruction SSRA, vector variant 2020-04-22 20:46:14 +01:00
MerryMage
f58aba9871 A64: Implement SIMD instruction SSHR, vector variant 2020-04-22 20:46:14 +01:00
MerryMage
715ae1c229 IR: Implement VectorArithmeticShiftRight 2020-04-22 20:46:14 +01:00
MerryMage
653c82d8f0 impl: Improve Vpart setter 2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35 A64: Implement SIMD instructions XTN, XTN2 2020-04-22 20:46:13 +01:00
MerryMage
132c783320 IR: Implement VectorNarrow 2020-04-22 20:46:13 +01:00
MerryMage
1423584f9f constant_pool: Allow for 128-bit constants 2020-04-22 20:46:13 +01:00
MerryMage
69de50a878 emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage
cbc9f361b0 IR: Implement VectorSub 2020-04-22 20:46:13 +01:00
MerryMage
3f93c77ace A64: Implement SIMD instruction USRA, vector variant 2020-04-22 20:46:13 +01:00
MerryMage
fb9d20f27f A64: Implement SIMD instruction USHR, vector variant 2020-04-22 20:46:13 +01:00
MerryMage
b22c5961f9 IR: Implement VectorLogicalShiftRight 2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b A64: Implement SIMD instructions USHLL, USHLL2 2020-04-22 20:46:13 +01:00
MerryMage
59ace60b03 IR: Implement VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage
d3a4e1efe2 IR: Vector instructions now take esize argument in emitter 2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23 A64: Implement SIMD instruction SHL 2020-04-22 20:46:13 +01:00
MerryMage
f6247125c0 IR: Implement VectorLogicalShiftLeft{8,16,32,64} 2020-04-22 20:46:13 +01:00
MerryMage
15e8231f24 opcodes: Sort vector IR opcodes alphabetically 2020-04-22 20:46:13 +01:00
MerryMage
d74f4e35f6 block_of_code: Increase constant pool size 2020-04-22 20:46:13 +01:00
MerryMage
e69288f803 devirtualize: MinGW uses Intanium MFP ABI 2020-04-22 20:46:13 +01:00
MerryMage
ad428cbd7a callback: Properly handle calls with return pointers and simplify interface 2020-04-22 20:46:13 +01:00
FernandoS27
15871910af Implemented BSL, BIC, BIT and BIF vector instructions 2020-04-22 20:46:13 +01:00
MerryMage
7a87e3fc55 devirtualize: Handle Windows ABI 2020-04-22 20:46:13 +01:00
MerryMage
ba4a779c62 A32/decoder/arm: bug: Correct bitstring for SRS 2020-04-22 20:46:13 +01:00
MerryMage
f808a0fbde devirtualize: Devirtualize Itanium ABI MFPs at runtime 2020-04-22 20:46:13 +01:00
MerryMage
afe16fa0f3 cast_util: Add BitCast and BitCastPointee 2020-04-22 20:46:13 +01:00
Lioncash
4e33629b0e A64: Move SDIV and UDIV out of data_processing_multiply.cpp 2020-04-22 20:46:13 +01:00
Lioncash
35a29a9665 A64: Implement ZIP1 2020-04-22 20:46:13 +01:00
FernandoS27
586854117b Implemented UMULH and SMULH instructions 2020-04-22 20:46:13 +01:00
MerryMage
1a7b7b541a A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
2020-04-22 20:46:13 +01:00
MerryMage
8ab7d8175c impl: Add AdvSIMDExpandImm 2020-04-22 20:46:13 +01:00
MerryMage
ea69cb4474 A64: Implement SUB (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage
4c5871d5d5 A64: Implement ADD (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage
2a0850c068 A64: Reorganize decoder tables (some vector entries were grouped with scalar entries) 2020-04-22 20:46:13 +01:00
MerryMage
7b33772ac6 A64: Implement BIC (vector, register) 2020-04-22 20:46:13 +01:00
MerryMage
eb5591859c A64: Implement FMOV (general) 2020-04-22 20:46:13 +01:00
MerryMage
dd88cee15a translate/impl: Add Vpart 2020-04-22 20:46:13 +01:00
MerryMage
cc9efd13c9 A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR 2020-04-22 20:46:13 +01:00
MerryMage
81713c2b77 A64: Implement FCCMPE 2020-04-22 20:46:13 +01:00
MerryMage
ef906dbbfa A64: Implement FCCMP 2020-04-22 20:46:13 +01:00
MerryMage
44c3c2312a a64_jitstate: Remove unnecessary FPSCR_nzcv member 2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2 IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them 2020-04-22 20:46:13 +01:00
Lioncash
2ee39d6b36 A64: Implement FMOV (register) 2020-04-22 20:46:13 +01:00
MerryMage
b02b861242 A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR 2020-04-22 20:46:13 +01:00
Lioncash
5a65313236 A64: Implement CCMP (immediate) 2020-04-22 20:46:13 +01:00
Lioncash
ab4664de61 A64: Implement CCMN (immediate) 2020-04-22 20:46:13 +01:00
Lioncash
a6c6539109 A64: Implement CCMP (register) 2020-04-22 20:46:13 +01:00
Lioncash
22632db337 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement 2020-04-22 20:46:13 +01:00
MerryMage
c5033b5dda A64: Implement CCMN (register) 2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe IR: Add ConditionalSelectNZCV instruction 2020-04-22 20:46:13 +01:00
MerryMage
4491746eae A64: Implement FNEG 2020-04-22 20:46:13 +01:00
MerryMage
db958061a3 A64: Implement FABS 2020-04-22 20:46:13 +01:00
MerryMage
8765b421b7 A64: Implement FCSEL 2020-04-22 20:46:13 +01:00
MerryMage
7e82d8eede A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage
2409e5d082 A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage
b173fcf34e backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register) 2020-04-22 20:46:13 +01:00
Lioncash
d040920727 Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7 A64: Implement AESD 2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7 A64: Implement AESE 2020-04-22 20:46:13 +01:00
MerryMage
68f46c8334 backend_x64: Use a reference to BlockOfCode instead of a pointer 2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
0bb4474fb9 A64: Implement INS (general) 2020-04-22 20:46:13 +01:00
MerryMage
d13704fdef A64: Implement INS (element) 2020-04-22 20:46:13 +01:00
MerryMage
0642d49919 A64: Implement SMOV 2020-04-22 20:46:13 +01:00
MerryMage
5297027ebe A64: Implement UMOV 2020-04-22 20:46:13 +01:00
MerryMage
47661b746b basic_block: Fix bogus GCC maybe-uninitialized warning 2020-04-22 20:46:13 +01:00
MerryMage
1fb0957aa3 A64: Implement FCVT 2020-04-22 20:46:13 +01:00
MerryMage
ca38225e08 fuzz_with_unicorn: Skip instructions that need to be interpreted 2020-04-22 20:46:13 +01:00
MerryMage
4be55b8b84 A64: Implement FMOV (scalar, immediate) 2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51 A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) 2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2 A64: Implement FCMP, FCMPE 2020-04-22 20:46:13 +01:00
MerryMage
75b8a76630 a64_jitstate: A64 does not have a seperate FPSCR.NZCV 2020-04-22 20:46:13 +01:00