Lioncash
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b48fb8ca6b
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A64: Implement PMUL
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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affa312d1d
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ir: Add opcode for performing polynomial multiplication
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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dd4ac86f8e
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A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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28b38916a8
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A64: Implement FCVTZS (vector, integer), single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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507bcd8b8b
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IR: Implement FPVectorTo{Signed,Unsigned}Fixed
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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8f75a1fe04
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fp/info: Replace constant value generators with FPValue
Instead of having multiple different functions we can just have one.
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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da261772ea
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emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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a0d6f0de57
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emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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c778c7b868
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A64: Implement FMAX's vector single and double precision variants
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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009879d92b
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A64: Implement FMIN's vector single and double precision variants
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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7b03da86c2
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IR: Implement FPVector{Max,Min}
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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e76e1186bb
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FPRecipEstimate: Move offset out of function
MSVC has weird lambda capturing rules.
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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ddcff86f9c
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microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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10de36394e
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A64: Implement FRECPS, vector/scalar single/double variants
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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901bd9b4e2
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IR: Implement FPRecipStepFused, FPVectorRecipStepFused
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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f66f61d8ab
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A64: Implement FRECPE, vector single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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939f5f5c7a
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IR: Implement FPVectorRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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27c73dd56a
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A64: Implement FRECPE, scalar single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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fc2d33ae7b
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IR: Implement FPRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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c1dcfe29f7
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IR: Implement FPRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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7a673a8a43
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fp: Change FPUnpacked to a normalized representation
Having a known position for the highest set bit makes writing algorithms easier
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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680395a803
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fuzz_with_unicorn: Disable testing of FDIV
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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3fe45c6d8e
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block_of_code: Add ABI_PARAMS array
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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642b6c31d2
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A64: Implement MLA, MLS (by element), vector single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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0de37b11ad
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A64: Implement FMLS (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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64c2f698a2
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emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
MSVC doesn't like dealing with auto return types
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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2ef59b4f03
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emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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04f325a05e
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IR: Implement FPVectorNeg
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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934132e0c5
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A64: Implement FMLA (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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771a4fc20b
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IR: Implement FPVectorMulAdd
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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3218bb9890
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emit_x64_vector_floating_point: Standardize naming scheme
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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8f72be0a02
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emit_x64_floating_point: Simplify indexers
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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25b28bb234
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emit_x64_vector_floating_point: Simplify EmitVectorOperation*
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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1edd0125b2
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mp: rename mp.h to mp/function_info.h
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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0921678edb
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emit_x64_vector: Slightly improve ArithmeticShiftRightByte
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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43407c4bb4
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emit_x64_vector: Simplify VectorShuffleImpl
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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ecbf9dbae5
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IR: Implement A64OrQC
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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f0fecf2615
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A64: Implement UQSHRN, UQRSHRN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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8f4c1a8558
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emit_x64_vector: -0x80000000 isn't -0x80000000
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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b455b566e7
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A64: Implement UQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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e686a81612
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emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
Allows non-SSE4.1 to produce the correct FPSR.QC flag
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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3874cb37e3
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A64: Implement SQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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8ef114d48f
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emit_x64_vector: packusdw reqiures SSE4.1
In EmitVectorSignedSaturatedNarrowToUnsigned32.
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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712c6c1d7e
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A64: Implement SQSHRUN, SQRSHRUN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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c5722ec963
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simd_shift_by_immediate: Simplify ShiftRight
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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f020dbe4ed
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A64: Implement SQXTUN
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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6918ef7360
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microinstruction: Reorganize FPSCR related instruction queries
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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a639fa5534
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microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
These were forgotten when the opcodes were added.
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2020-04-22 20:46:22 +01:00 |
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Lioncash
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3ca18d8a6d
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u128: Make Bit() a const-qualified member function
This function doesn't modify the struct members, so it can be made
const.
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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b2e4c16ef8
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A64: Implement FRSQRTS (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
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