Commit graph

397 commits

Author SHA1 Message Date
MerryMage
fe15cbd50e translate_arm/parallel: Detect UNPREDICTABLE instructions 2016-08-19 00:59:07 +01:00
MerryMage
2119dfc926 translate_arm/multiply: MLA is UNPREDICTABLE when Ra == R15 2016-08-19 00:59:05 +01:00
MerryMage
0d0f4b1b4f translate_arm/load_store: Correct implementation for LDM* 2016-08-19 00:59:04 +01:00
MerryMage
4acc481463 translate_arm/load_store: Handle unpredictable instructions
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
2016-08-19 00:59:02 +01:00
MerryMage
5869e79b9c translate_arm: Simplify EmitImmShift and EmitRegShift 2016-08-19 00:21:31 +01:00
Lioncash
fe9329ef3e intrusive_list: Add list class type definitions; extend iterator interface
Adds type definitions, and extends the list interface to support all
standard library forms of iterator creation.
2016-08-18 23:47:26 +01:00
Lioncash
95a83543f2 intrusive_list: Get rid of unnecessary static_casts
The only valid objects to add to the list are those that inherit from
IntrusiveListNode. Therefore anything being added to the list that isn't
inheriting from it will cause compilation to fail.
2016-08-18 23:47:26 +01:00
Lioncash
67509935f6 intrusive_list: Eliminate need for separate const iterator construct
This generalizes the regular iterator to be compatible with both use
cases. Passing in the list instance directly isn't needed, because the
only way you'd ever get a valid instantiation of an iterator is from a
list instance itself.
2016-08-18 23:47:26 +01:00
MerryMage
b8cf43c43e translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions 2016-08-18 18:23:05 +01:00
MerryMage
efc8d2f772 arm_translator: NV conditional is obsolete 2016-08-18 18:21:48 +01:00
MerryMage
5f7d940fde disassemble_arm: Partially implement coprocessor and hint instructions 2016-08-18 18:21:16 +01:00
MerryMage
36a916a766 decoder/arm: Correct NOP decoder 2016-08-18 18:20:29 +01:00
MerryMage
e9e7ac6e65 decoder/arm: Correct PLD decoder for v6K 2016-08-18 18:19:34 +01:00
MerryMage
269160ef0d emit_x64: Clear RSB-related caches when ClearCache() is called 2016-08-18 18:18:44 +01:00
MerryMage
1a3f3ac435 emit_x64: Correct behaviour of PackedOperation for immediate argument
x64 MOVD_xmm does not support an immediate oparg
2016-08-18 18:17:17 +01:00
MerryMage
b2de47954b EmitX64: Emit correct cycle count on cond failure 2016-08-18 18:16:18 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
Lioncash
9690d1423d intrusive_list: explicitly default relevant constructors 2016-08-17 20:46:11 +01:00
Lioncash
cbd99e4367 jitstate: Use std::array's fill() in ResetRSB
Performs the equivalent behavior
2016-08-17 10:10:43 +01:00
Lioncash
74ee92ee38 jitstate: const correctness
GetReturnFromRunCodeAddress is const qualified, so this can accept a const
pointer. This also allows for making the constructor accept a const
pointer as well.
2016-08-17 10:10:43 +01:00
Lioncash
9ed9f4c565 mp: Generalize function information retrieval
Generalizes MemFnInfo to be compatible with all function types.
Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.
2016-08-17 10:08:40 +01:00
Lioncash
439619c827 reg_alloc: Make GetRegLoc return by const reference
Considering a HostLocInfo instance houses a std::vector, every time this
function is called can cause a potential heap allocation.

This can be somewhat unnecessary because this function is only used to query
for information we already have.

Considering this is used by several other internal query functions such as
IsRegisterOccupied, IsRegisterAllocated, and IsLastUse, this will result
in better codegen (returning an address is just 3 instructions excluding
the ret instruction for returning, meanwhile heap alloc can be 60+).

This also renames the function to have the same name as its non-const
counterpart, since overloading will just select the correct function
instead of putting that onus on the developer.
2016-08-17 10:08:08 +01:00
MerryMage
0ebb572e2d Optimization: Make RSB a ring buffer instead of a stack 2016-08-15 15:48:22 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1 Optimization: Implement terminal LinkBlockFast 2016-08-15 14:33:17 +01:00
MerryMage
624e84fa09 Optimization: Tweak RSB 2016-08-15 14:08:06 +01:00
MerryMage
070298b948 Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect 2016-08-15 13:21:58 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
bunnei
30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
MerryMage
9c82a12f8f ir_opt: Update VerificationPass to current IR 2016-08-13 18:39:49 +01:00
MerryMage
8fc21f481a RegAlloc: Handle case when def is unused 2016-08-13 01:55:03 +01:00
MerryMage
d43d97b990 EmitX64/EmitPushRSB: Assert that patch location is of correct size 2016-08-13 00:52:31 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
3808938c98 Fix SETEND 2016-08-11 19:15:58 +01:00
bunnei
218980cf69 load_store: Implement LDRSB and LDRSH. 2016-08-11 17:18:20 +01:00
MerryMage
0e5593ba62 TranslateArm: Implement SETEND 2016-08-11 17:15:33 +01:00
MerryMage
8964b38cf9 IR/DumpBlock: Print references to ExtRegs 2016-08-11 17:15:02 +01:00
MerryMage
b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode 2016-08-10 16:43:37 +01:00
MerryMage
945498a16a DisassemblerArm: Disassemble SETEND 2016-08-10 16:15:07 +01:00
bunnei
8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
d921390928 TranslateArm: Add santity check to see if we've emitted a terminal instruction 2016-08-09 22:47:41 +01:00
MerryMage
2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
MerryMage
29d30bf931 Interface: Added Jit::Reset to reset CPU state 2016-08-09 22:45:54 +01:00
MerryMage
82f42d065f DisassemblerArm: Implemented disassembly of STR*/LDR* instructions 2016-08-09 22:44:42 +01:00