MerryMage
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624e84fa09
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Optimization: Tweak RSB
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2016-08-15 14:08:06 +01:00 |
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MerryMage
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070298b948
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Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect
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2016-08-15 13:21:58 +01:00 |
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MerryMage
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e164ede4dc
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TranslateArm: Implement MRS, MSR (imm), MSR (reg)
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2016-08-15 11:50:49 +01:00 |
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MerryMage
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d43d97b990
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EmitX64/EmitPushRSB: Assert that patch location is of correct size
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2016-08-13 00:52:31 +01:00 |
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MerryMage
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960d14d18e
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Optimization: Implement Return Stack Buffer
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2016-08-13 00:10:23 +01:00 |
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bunnei
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8e68e6fdd9
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TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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4b09c0d032
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TranslateArm: Implement QADD8 and UQADD8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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127fbe99cb
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TranslateArm: Implement QSUB8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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86fe29c6d2
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TranslateArm: Implement UQSUB8.
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2016-08-12 19:00:44 +01:00 |
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MerryMage
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1029fd27ce
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Update documentation (2016-08-12)
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2016-08-12 18:17:31 +01:00 |
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MerryMage
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df39308e03
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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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Tillmann Karras
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5d26899ac9
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Add simplified LogicalShiftRight64 IR opcode
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2016-08-08 22:27:05 +01:00 |
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Tillmann Karras
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ccb2aa96a5
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Add support for the APSR.Q flag
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2016-08-08 22:27:04 +01:00 |
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MerryMage
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975f011fc0
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BackendX64/RegAlloc: Do not allocate RSP for guest use
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2016-08-08 16:01:07 +01:00 |
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MerryMage
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abd113f160
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EmitX64: Renamed patch_jmp_locations to patch_jg_locations
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2016-08-08 15:56:07 +01:00 |
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MerryMage
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52fa998e6b
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EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags
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2016-08-07 22:47:43 +01:00 |
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MerryMage
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04c1a0d2de
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EmitX64: Switch MXCSR when switching to interpreter
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2016-08-07 22:47:17 +01:00 |
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MerryMage
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a32063fa60
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EmitX64: Implement block linking
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2016-08-07 22:11:39 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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MerryMage
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aba705f6b9
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BackendX64: Merge Routines into BlockOfCode
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2016-08-07 18:08:48 +01:00 |
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MerryMage
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0f412247ed
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VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
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MerryMage
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3f1345a1a5
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VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
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MerryMage
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12e7f2c359
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VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
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MerryMage
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97b5fa173f
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VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
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MerryMage
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ce6b5f8210
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VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
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MerryMage
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f88b1b4c2e
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FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask
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2016-08-07 01:10:19 +01:00 |
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Tillmann Karras
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846d07d7b5
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Add Sub64 opcode
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2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
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b9f4f1ed0f
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Add carry support to MostSignificantWord
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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856298577d
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EmitX64: Don't give MOVSX or MOVZX an immediate oparg
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2016-08-06 01:03:39 +01:00 |
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MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
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MerryMage
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4c0a85f3b3
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EmitX64: Correct EmitPack2x32To1x64 implementation
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2016-08-05 18:43:24 +01:00 |
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MerryMage
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d80dcc5367
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BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
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2016-08-05 15:27:29 +01:00 |
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MerryMage
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b4aa01ccf4
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Merge remote-tracking branch 'tilkax/master'
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2016-08-05 14:14:06 +01:00 |
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MerryMage
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94e75ad32f
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BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
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2016-08-05 14:11:27 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
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Tillmann Karras
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72c503016c
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Fix Pack2x32To1x64
Not sure how to fix this properly.
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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3fdc093d10
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Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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4414ec5bc8
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RegAlloc: Allow allocation of XMM registers
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2016-08-02 13:46:12 +01:00 |
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MerryMage
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864081d1a0
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BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
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2016-08-02 12:00:11 +01:00 |
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MerryMage
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93af160c97
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arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
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2016-08-02 11:54:02 +01:00 |
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MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
|
5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
|
2016-07-20 15:34:17 +01:00 |
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MerryMage
|
3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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MerryMage
|
e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
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MerryMage
|
8a310777a1
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backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
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2016-07-18 20:01:48 +01:00 |
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