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78 commits

Author SHA1 Message Date
MerryMage
6adc554b53 jit_state: Hide cpsr implementation 2020-04-22 20:26:40 +01:00
MerryMage
256749910f Add AddTicks and GetTicksRemaining callbacks 2020-04-22 20:26:12 +01:00
MerryMage
f734d7000e fuzz_arm: Test SEL alongside packed instructions 2020-04-22 20:26:07 +01:00
MerryMage
814e378249 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2020-04-22 20:26:07 +01:00
MerryMage
c6c980dfd7 fuzz_arm: Add vsub test 2017-04-02 12:38:38 +01:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
MerryMage
2449468ede fuzz_arm: Dump state when exception is thrown 2017-02-25 11:55:27 +00:00
MerryMage
2447f2f360 callbacks: Factorize memory callbacks into inner structure 2017-01-30 21:42:51 +00:00
Fernando Sahmkow
70f4235ee9 Implement UXTAB16 (#78) 2016-12-29 12:15:18 +00:00
MerryMage
36082087de callbacks: Read code using MemoryReadCode callback 2016-12-21 21:39:14 +00:00
MerryMage
b1df70578f fuzz_arm: Add test cases for saturation instructions 2016-12-21 19:51:25 +00:00
MerryMage
410e84434e fuzz_arm: Add tests for QASX, QSAX, UQASX, UQSAX 2016-12-20 21:52:38 +00:00
FernandoS27
8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage
975987f38e fuzz_arm: Add test for edge-case of UASX instruction 2016-12-20 20:04:38 +00:00
MerryMage
821b26e9d2 fuzz_arm: Add test for edge-case of SHSAX instruction 2016-12-20 19:12:21 +00:00
MerryMage
96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage
5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00
MerryMage
370f654590 fuzz_arm: Add tests for parallel add/subtract (modulo) 2016-12-04 20:51:12 +00:00
Sebastian Valle
cda25c12b3 Added tests for the ARM parallel halving instructions. (#49) 2016-11-26 17:24:57 +00:00
Sebastian Valle
32615d0eff Implemented the PKHTB and PKHBT instructions with tests. (#40) 2016-11-23 21:45:18 +00:00
Sebastian Valle
d589c63107 Implemented the ARM SEL instruction, with tests. (#39) 
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
 2016-11-23 18:14:07 +00:00
MerryMage
5c8bf5a15d callbacks: CallSVC returns void 2016-09-05 19:15:45 +01:00
Mat M
6d53bb6d7e arm_types: Split out LocationDescriptor (#20) 
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
 2016-09-05 11:54:09 +01:00
Mat M
8c4df46580 FPSCR: Make value constructor explicit (#13) 
Maintains consistency between the PSR helper.
 2016-09-03 12:48:31 +01:00
Mat M
6ec651498d arm: Add PSR helper type (#3) 2016-09-02 17:34:33 +01:00
bunnei
728b4ca0d4 tests: Fix compile errors. (#4) 2016-09-02 08:51:03 +01:00
MerryMage
4321e829d1 callbacks: Add user_arg argument to InterpreterFallback 2016-09-01 02:00:08 +01:00
MerryMage
ed3a686d1d Implement public header files 2016-08-26 00:44:50 +01:00
MerryMage
130b5510a6 tests/fuzz_arm: Fix MSVC conversion warnings 2016-08-25 17:46:22 +01:00
Lioncash
0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage
7d181f46ce fuzz_arm: Print more than one IR basic block on failure 2016-08-25 13:00:46 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
MerryMage
74246cc3bf tests/fuzz_arm: Randomize rounding mode in initial_fpscr 2016-08-22 15:54:22 +01:00
MerryMage
f014f3b7d4 tests/fuzz_arm: Update FPSCR in InterpreterFallback 2016-08-22 15:54:21 +01:00
Tillmann Karras
dad7724b86 TranlateArm: implement remaining multiplies 
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
 2016-08-19 01:08:38 +01:00
MerryMage
4acc481463 translate_arm/load_store: Handle unpredictable instructions 
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
 2016-08-19 00:59:02 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
bunnei
30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode 2016-08-10 16:43:37 +01:00
bunnei
8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
b3bb1d5048 Tests: Tidy up ARM fuzz tests 2016-08-07 21:55:38 +01:00
MerryMage
4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage
1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00
MerryMage
3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00