MerryMage
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f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c9b4f0114
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A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1dd2b33b87
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A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5eac3abf52
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A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3afd2fcbad
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A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e7041d7196
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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faeb77e8c4
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A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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653c82d8f0
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impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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3f93c77ace
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A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ba4a779c62
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A32/decoder/arm: bug: Correct bitstring for SRS
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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4e33629b0e
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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586854117b
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Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8ab7d8175c
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impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ea69cb4474
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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eb5591859c
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A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cc9efd13c9
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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2ee39d6b36
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A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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5a65313236
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab4664de61
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A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a6c6539109
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A64: Implement CCMP (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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22632db337
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4491746eae
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A64: Implement FNEG
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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db958061a3
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A64: Implement FABS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8765b421b7
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7e82d8eede
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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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56bc7825ef
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0bb4474fb9
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A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d13704fdef
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A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0642d49919
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A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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5297027ebe
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A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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47661b746b
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1fb0957aa3
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A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ca38225e08
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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a07c05ea51
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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af1384d700
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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cc0eb18a0b
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A32: data_processing: Remove !S assertions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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865a30eb0d
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A32: Implement BKPT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f023bbb893
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A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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d7044bc751
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assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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52268298a8
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a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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6fc228f7fd
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ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
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MerryMage
|
e01b500aea
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ir_emitter: Allow the insertion point for new instructions to be set
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7734cf1050
|
A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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88ae7fce52
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
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A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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ba3d6da0c8
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load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
d5283e46e8
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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94383fd934
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microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
589ad7232f
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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
ae880d8391
|
A64: Fix bugs and address review comments
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
3aeb7ca50c
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Add missing returns
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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285fd22c30
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IR: Add IR instruction VectorZeroUpper
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2020-04-22 20:44:37 +01:00 |
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