MerryMage
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78a047f0f9
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A64: Implement EXT
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
8bba37089e
|
A64: Implement UADDW
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2020-04-22 20:46:15 +01:00 |
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Lioncash
|
94f0fba16b
|
A64: Implement SHA1H
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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6177c2c63d
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CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
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2020-04-22 20:46:15 +01:00 |
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Lioncash
|
7a66224d9a
|
A64: Implement EOR3 and BCAX
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
fd8f4c1195
|
A64: Implement UCVTF (vector, integer), scalar variant
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
be57608353
|
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
bd2b415850
|
A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
e97581d063
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fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
5edd623b9d
|
Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
afe16fa0f3
|
cast_util: Add BitCast and BitCastPointee
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
c5033b5dda
|
A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2409e5d082
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
56bc7825ef
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
99d8ebe4d5
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ed2bedec43
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
bafb39ebc5
|
A64: Add Disassemble method
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
6fc228f7fd
|
ir_opt: Add A64 Get/Set Elimination Pass
|
2020-04-22 20:46:12 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
5281d3c6d5
|
CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
30936f5e94
|
travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
db30e02ac8
|
emit_x64: Extract BlockRangeInformation, remove template parameter
|
2020-04-22 20:44:36 +01:00 |
|
MerryMage
|
a554e4a329
|
backend_x64: Split emit_x64
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
c1a25bfc2f
|
A64: Implement MADD and MSUB
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
ae5dbcbed6
|
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
4d8f4aa8af
|
A64: Implement ASRV, LSLV, LSRV, and RORV
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
a63fc6c89b
|
A64: Implement ADD (vector, vector)
|
2020-04-22 20:42:46 +01:00 |
|
Thomas Guillemard
|
896cf44f96
|
A64: Implement REV, REV32, and REV16 (#126)
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
144b629d8a
|
A64: Implement CSEL
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
9f57283a30
|
A64: Implement SBFM, BFM, UBFM
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
cdbc8d07a5
|
A64: Implement MOVN, MOVZ, MOVK
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
c6a091d874
|
A64: Optimization: Merge interpret blocks
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
b34c6616d4
|
A64/decoder: Split decoder data from header
|
2020-04-22 20:42:45 +01:00 |
|