Lioncash
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8fa9849c25
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unicorn: Use static_cast instead of reinterpret_cast
It's well-defined to cast from void* back to the original pointer type.
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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ba3d6da0c8
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load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d5283e46e8
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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4ce9c65cfb
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reg_alloc: Use std::exchange
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2020-04-22 20:44:38 +01:00 |
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Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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cf824fb2b2
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unicorn_load: Minor Windows-related changes
- Add missing include
- Fix a potential compilation issue where the constructor wouldn't be able to execute, as it would be private.
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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a8ed248a13
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tests/A64: Test memory writes
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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94383fd934
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microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d124a1d761
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emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
For CPUs that didn't support SSE4.1, this was a bug.
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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f1057aa362
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tests: Fix truncation in GetFpcr()
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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589ad7232f
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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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ae880d8391
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A64: Fix bugs and address review comments
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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3aeb7ca50c
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Add missing returns
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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41e6e659c5
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A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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01a26fa644
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fixup: travis: Test with disabled CPU feature detection
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2020-04-22 20:44:37 +01:00 |
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Lioncash
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5281d3c6d5
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CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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30936f5e94
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travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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285fd22c30
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IR: Add IR instruction VectorZeroUpper
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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da3e9a5704
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a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
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2020-04-22 20:44:37 +01:00 |
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FernandoS27
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ab84524806
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Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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6033b05ca6
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A64: Implement LDR/STR (immediate, SIMD&FP)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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f698848e26
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IR: Add IR instructions A64Memory{Read,Write}128
Add the Windows ABI implementation
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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e1df7ae621
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IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
e00a522cba
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IR: Add IR instruction VectorGetElement{8,16,32,64}
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
28ccd85e5c
|
IR: Add IR instruction ZeroExtendToQuad
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
af848c627d
|
block_of_code: Add ABI_RETURN2
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
1749780929
|
interface: Move Vector typedef to config.h
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
33bba6028c
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bit_util: bug: Infinite loop in HighestSetBit
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
793753bf63
|
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
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2020-04-22 20:44:37 +01:00 |
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Lioncash
|
8ee854232c
|
General: Default constructors and destructors where applicable
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2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
d1e4526e1c
|
ir_emitter: Remove unused includes
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2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
6f9216d544
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A64: Implement RBIT
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
9b0a21915f
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ir_emitted: Remove unimplemented IR instruction Unimplemented
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
db30e02ac8
|
emit_x64: Extract BlockRangeInformation, remove template parameter
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2020-04-22 20:44:36 +01:00 |
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MerryMage
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58c4a25527
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emit_x64: Use JitStateInfo
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2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
d4b05b28cf
|
A64: Implement CLS
This is not the cleanest implementation.
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
b8e26bfdc3
|
A64: Implement ADDP (vector)
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
eaf545877a
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IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
a554e4a329
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backend_x64: Split emit_x64
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
2a493f8b50
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fuzz_with_unicorn: Compare vectors
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2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
394bd57bb6
|
microinstruction: bug: Add missing opcodes
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2020-04-22 20:42:46 +01:00 |
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Lioncash
|
bb1c5bd3b2
|
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
c1a25bfc2f
|
A64: Implement MADD and MSUB
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b7c5055d42
|
A64: Implement CLZ
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b612782445
|
opcodes: Add 64-bit CountLeadingZeroes opcode
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2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
4c4efb2213
|
data_processing_register: Clean-up
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
ae5dbcbed6
|
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
4d8f4aa8af
|
A64: Implement ASRV, LSLV, LSRV, and RORV
|
2020-04-22 20:42:46 +01:00 |
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