MerryMage
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b4c586d5ef
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TranslateArm: VSTR: Correct behaviour in big-endian mode
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2016-08-10 16:43:37 +01:00 |
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bunnei
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8e8db6e137
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TranslateArm: Implement VSTR.
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2016-08-10 15:01:23 +01:00 |
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MerryMage
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df39308e03
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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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MerryMage
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d921390928
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TranslateArm: Add santity check to see if we've emitted a terminal instruction
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2016-08-09 22:47:41 +01:00 |
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MerryMage
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d0d51ba346
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TranslateArm: Implement STM, STMDA, STMDB, STMIB
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2016-08-08 22:49:11 +01:00 |
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MerryMage
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85549d7ae2
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TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
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2016-08-08 22:26:06 +01:00 |
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MerryMage
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edb236ab07
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Correct implementation of thumb16_SVC and arm_SVC
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2016-08-07 22:19:39 +01:00 |
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MerryMage
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4dcd1d1859
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Arm: BLX is UNPREDICTABLE when Rm is PC
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2016-08-07 20:50:33 +01:00 |
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MerryMage
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1af5bef32c
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TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
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2016-08-07 20:40:31 +01:00 |
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MerryMage
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939bb5c0cb
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TranslateArm: Implement NOP
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2016-08-07 20:08:31 +01:00 |
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MerryMage
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e48df9d8fd
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TranslateArm: Implement Hint instructions as NOPs
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2016-08-07 20:04:48 +01:00 |
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MerryMage
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3a465ba4a8
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VFP: Implement VLDR
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2016-08-07 19:59:35 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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MerryMage
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0f412247ed
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VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
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MerryMage
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cd8e7c0504
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VFP: Implement VNEG
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2016-08-07 12:04:21 +01:00 |
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MerryMage
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da33af5abe
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VFP: Implement VMLA, VMLS, VNMLA, VNMLS
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2016-08-07 11:49:06 +01:00 |
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MerryMage
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3f1345a1a5
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VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
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MerryMage
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12e7f2c359
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VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
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MerryMage
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97b5fa173f
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VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
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MerryMage
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ce6b5f8210
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VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
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MerryMage
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c35f06470f
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VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
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2016-08-06 23:01:18 +01:00 |
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MerryMage
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94b99f5949
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Common: Add an intrusive list implementation; remove use of boost::intrusive::list.
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2016-08-06 22:23:01 +01:00 |
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Tillmann Karras
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55204a80d0
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Implement SMMLA, SMMLS, SMMUL
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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b9f4f1ed0f
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Add carry support to MostSignificantWord
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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7915f97d98
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TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
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2016-08-06 20:42:06 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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8ff414ee0e
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Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
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2016-08-06 20:03:15 +01:00 |
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bunnei
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2448d52394
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load_store: Use correct types for LDR/STR.
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2016-08-05 20:51:32 -04:00 |
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bunnei
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8c2300d477
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arm: Implement LDRD reg/imm instructions.
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2016-08-05 20:05:02 -04:00 |
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bunnei
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72608b7af6
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arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
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2016-08-05 20:05:02 -04:00 |
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bunnei
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ec3a98cf95
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arm: Implement LDRH reg/imm instructions.
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2016-08-05 20:05:01 -04:00 |
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bunnei
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192a0fba7a
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arm: Implement LDRB reg/imm instructions.
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2016-08-05 20:05:00 -04:00 |
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bunnei
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dfb318f208
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arm: Implement STRD reg/imm instructions.
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2016-08-05 20:04:59 -04:00 |
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bunnei
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e931dc2496
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arm: Implement STRH reg/imm instructions.
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2016-08-05 20:04:58 -04:00 |
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bunnei
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9f77662b24
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arm: Implement STRB reg/imm instructions.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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caab1bbc7c
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arm: Implement STR reg/imm instructions.
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2016-08-05 20:04:56 -04:00 |
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bunnei
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b09ecb4532
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arm: Implement LDR reg/imm instructions.
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2016-08-05 20:04:55 -04:00 |
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Tillmann Karras
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fce8c86c90
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Implement RSB
somehow missed this earlier
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2016-08-05 02:13:26 +01:00 |
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Tillmann Karras
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eb2e6e8bea
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Implement some multiplies
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2016-08-05 02:09:54 +01:00 |
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bunnei
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691e4139fa
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arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
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30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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a875c0c720
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TranslateArm: Stub more ARM instructions
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2016-08-02 21:59:33 +01:00 |
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MerryMage
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6097a21955
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TranslateArm: Reorganisation - Split visitor into multiple .cpp files
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2016-08-02 11:54:04 +01:00 |
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MerryMage
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93af160c97
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arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
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2016-08-02 11:54:02 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
|
95588d3faa
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Fix Thumb BLX (imm), BL (imm) for negative immediates
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2016-07-18 22:48:23 +01:00 |
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MerryMage
|
3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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