MerryMage
8bba37089e
A64: Implement UADDW
2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888
A64: Implement FMUL (vector)
2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd
A64: Implement UABA
...
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e
A64: Implement UABD
2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce
ir: Add opcodes for performing vector unsigned absolute differences
2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3
ir_emitter: Make immediate member functions const qualified
...
These don't modify class state
2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e
IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords
...
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b
A64: Implement SHA1H
...
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b
A64: NOP immediate variant of PRFM
...
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276
A64: system: Use an enum class for MRS/MSR register encodings
...
Reduces the need to manually write out the register bit encodings repeatedly.
2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d
A64: Implement REV64
2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3
A64: Implement REV32 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6b0010c940
ir: Add IR opcodes for emitting vector shuffles
...
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0
A64: Implement REV16 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a
A64: Implement EOR3 and BCAX
2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2
impl: Update PC when raising exception
2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad
A64: Implement FDIV (vector)
2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68
system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d
Correct FPSR and FPCR
2020-04-22 20:46:15 +01:00
MerryMage
147284427b
A64: Implement USHL
2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195
A64: Implement UCVTF (vector, integer), scalar variant
2020-04-22 20:46:15 +01:00
MerryMage
be57608353
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676
A64: Implement system register TPIDR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e
A64: Implement system registers FPCR and FPSR
2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d
A64: Implement system register CNTPCT_EL0
2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00
A64: Implement system register CTR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b
A64: Implement NEG (vector)
2020-04-22 20:46:15 +01:00
MerryMage
710d09471b
IR: Add IR instruction ZeroVector
2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b
A64: Implement FMINNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07
A64: Implement FMAXNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
bd2b415850
A64: Implement ADDP (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0
A64: Implement DUP (element), scalar variant
2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41
A64: Implement FMAX (scalar), FMIN (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198
A64: Implement FSQRT (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
01c1e9017e
T32: Add initial decoder list
2020-04-22 20:46:14 +01:00
MerryMage
ccf7df057b
simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab
decoder/a64: Rearrange SIMD two-register misc decoders
2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06
A64: Implement CMGE (register)
2020-04-22 20:46:14 +01:00
MerryMage
9d85991906
A64: Implement CMHI, CMHS
2020-04-22 20:46:14 +01:00
MerryMage
e2b9b7c5b0
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73
A64: Implement SMAX, SMIN, UMAX, UMIN
2020-04-22 20:46:14 +01:00
MerryMage
47c0ad0fc8
IR: Implement Vector{Max,Min}{Signed,Unsigned}
2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f
A64: Implement CMGT (register)
2020-04-22 20:46:14 +01:00
MerryMage
f4775910f5
IR: Implement VectorGreaterSigned
2020-04-22 20:46:14 +01:00
MerryMage
1f5b3bca43
Exclusive fixups
...
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
2020-04-22 20:46:14 +01:00
MerryMage
8698f057d0
A64: Implement STXP, STLXP, LDXP, LDAXP
2020-04-22 20:46:14 +01:00
MerryMage
2a6619d59c
A64: Implement CLREX
2020-04-22 20:46:14 +01:00
MerryMage
b7a2c1a7df
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2020-04-22 20:46:14 +01:00
MerryMage
8756487554
A64: Partially implement MRS
2020-04-22 20:46:14 +01:00