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163 commits

Author SHA1 Message Date
Merry
0ff8c375af Implement UHSUB8 and UHSUB16 (#48) 2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed Implement SHADD8 and SHADD16 (#47) 2016-11-26 18:12:29 +00:00
MerryMage
c0c1bb1094 Implemented UHADD16 2016-11-26 11:28:20 +00:00
Sebastian Valle
4d44474ad4 Implemented the ARM UHADD8 instruction. (#45) 
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
 2016-11-25 20:32:22 +00:00
MerryMage
b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
Mat M
6e0f27a500 types: Add helpers for determining single and doubleword extension registers (#26) 2016-09-07 12:08:35 +01:00
Mat M
5bc9ce544f arm_types: Move into arm folder (#25) 2016-09-06 00:52:33 +01:00
MerryMage
1f61a3d7bc jitstate: Rename fields s/guest_FPSCR/FPSCR/ 2016-09-05 14:42:21 +01:00
Mat M
6d53bb6d7e arm_types: Split out LocationDescriptor (#20) 
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
 2016-09-05 11:54:09 +01:00
Mat M
7f9a0c3c38 Remove unnecessary explicit includes (#16) 2016-09-03 21:48:03 +01:00
MerryMage
4321e829d1 callbacks: Add user_arg argument to InterpreterFallback 2016-09-01 02:00:08 +01:00
MerryMage
3b5c43b427 Optimization: Read page-table directly for memory access 2016-09-01 00:58:02 +01:00
Lioncash
ea6a4e82b5 block_of_code: Make CallFunction accept function pointers only 2016-08-31 21:51:44 +01:00
Lioncash
f2bf795876 intrusive_list: Interface changes 
- Remove the root pointer from iterators.

This is unnecessary, since the only way to get a valid iterator is
either from a node itself (it transiently becomes an iterator via the
underlying interface), or through the iterator interface for the list.
This should also result in better code generation, as each increment or
decrement of an iterator is now branchless.

- Remove iterator_to

This is actually a pretty dangerous function, since it would immediately
create an iterator into the list using the given item, even if it's not
actually part of the list. This was only left around due to lack of
type handling around constructors.

- Add other overloads for erase() and remove()

Now handles iterators, pointers, and references.
 2016-08-28 20:56:40 +01:00
MerryMage
7912a79fa5 emit_x64: align before emitting blocks 2016-08-27 11:04:43 +01:00
MerryMage
dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
MerryMage
814348371e emit_x64: EmitX64::Emit: block.Location() returns by value 2016-08-26 19:43:29 +01:00
MerryMage
4f6ea715b2 emit_x64: EmitX64::Emit doesn't need descriptor argument 2016-08-26 19:14:25 +01:00
Lioncash
32c24d2cb3 Use 'false' instead of '0' in asserts 2016-08-26 18:52:08 +01:00
MerryMage
065c53ebfc emit_x64: Make ZeroIfNaN64 branchless 2016-08-26 15:23:08 +01:00
MerryMage
656d4f7252 emit_x64: inhibit_emission is obsolete 
Not used anymore; unused ever since intrusive lists were introduced.
 2016-08-25 23:24:16 +01:00
MerryMage
4322c0907c microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables 2016-08-25 21:08:47 +01:00
MerryMage
922d1fd198 Merge branch 'xbyak' 2016-08-25 16:54:48 +01:00
MerryMage
e32812cd00 Port x64 backend to xbyak 2016-08-25 16:18:17 +01:00
Lioncash
0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage
dc26afbd7e translate_arm: Translate more than one conditional instruction in a block 2016-08-25 13:05:33 +01:00
MerryMage
22cca5ff72 emit_x64: Actually advance RSB pointer 2016-08-24 23:19:47 +01:00
Lioncash
eba3a06d80 frontend: Introduce FPSCR register helper class 
Encapsulates all of the FPSCR state.
 2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash
1abe881921 basic_block: Add proxy member functions for the instruction list 
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).

So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.

Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
 2016-08-22 13:44:56 +01:00
MerryMage
269160ef0d emit_x64: Clear RSB-related caches when ClearCache() is called 2016-08-18 18:18:44 +01:00
MerryMage
1a3f3ac435 emit_x64: Correct behaviour of PackedOperation for immediate argument 
x64 MOVD_xmm does not support an immediate oparg
 2016-08-18 18:17:17 +01:00
MerryMage
b2de47954b EmitX64: Emit correct cycle count on cond failure 2016-08-18 18:16:18 +01:00
MerryMage
0ebb572e2d Optimization: Make RSB a ring buffer instead of a stack 2016-08-15 15:48:22 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1 Optimization: Implement terminal LinkBlockFast 2016-08-15 14:33:17 +01:00
MerryMage
624e84fa09 Optimization: Tweak RSB 2016-08-15 14:08:06 +01:00
MerryMage
070298b948 Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect 2016-08-15 13:21:58 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
MerryMage
d43d97b990 EmitX64/EmitPushRSB: Assert that patch location is of correct size 2016-08-13 00:52:31 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
Tillmann Karras
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
MerryMage
975f011fc0 BackendX64/RegAlloc: Do not allocate RSP for guest use 2016-08-08 16:01:07 +01:00
MerryMage
abd113f160 EmitX64: Renamed patch_jmp_locations to patch_jg_locations 2016-08-08 15:56:07 +01:00
MerryMage
52fa998e6b EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags 2016-08-07 22:47:43 +01:00
MerryMage
04c1a0d2de EmitX64: Switch MXCSR when switching to interpreter 2016-08-07 22:47:17 +01:00
MerryMage
a32063fa60 EmitX64: Implement block linking 2016-08-07 22:11:39 +01:00
MerryMage
a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage
aba705f6b9 BackendX64: Merge Routines into BlockOfCode 2016-08-07 18:08:48 +01:00
MerryMage
0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
f88b1b4c2e FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask 2016-08-07 01:10:19 +01:00
Tillmann Karras
846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
856298577d EmitX64: Don't give MOVSX or MOVZX an immediate oparg 2016-08-06 01:03:39 +01:00
MerryMage
640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage
4c0a85f3b3 EmitX64: Correct EmitPack2x32To1x64 implementation 2016-08-05 18:43:24 +01:00
MerryMage
d80dcc5367 BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64 2016-08-05 15:27:29 +01:00
MerryMage
b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage
94e75ad32f BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg} 2016-08-05 14:11:27 +01:00
MerryMage
ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras
72c503016c Fix Pack2x32To1x64 
Not sure how to fix this properly.
 2016-08-05 02:09:30 +01:00
Tillmann Karras
3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras
af27ef8d6c Optionally disassemble x86_64 code using LLVM 2016-08-05 02:08:41 +01:00
Tillmann Karras
2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
MerryMage
4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage
864081d1a0 BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR 2016-08-02 12:00:11 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage
8a310777a1 backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC 2016-07-18 20:01:48 +01:00
Subv
703a46ec99 Pass the current IR::Block by reference to the emitter. 
This avoids calling the copy constructor more times than needed.
 2016-07-18 11:27:33 -05:00
MerryMage
3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage
9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage
7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage
4ab4ca58f9 backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight 2016-07-14 09:02:27 +01:00
MerryMage
08e848044d backend_x64: Inline Routines::GenReturnFromRunCode into emitted code 2016-07-12 16:46:27 +01:00
MerryMage
8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage
09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00
MerryMage
1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage
d11df9067d Implement thumb1_BIC_reg 2016-07-10 10:44:45 +08:00
MerryMage
98a64a92b1 Implement thumb1_ORR_reg 2016-07-10 09:06:38 +08:00
MerryMage
8145b33882 Implemented thumb1_ROR_reg 2016-07-10 08:18:17 +08:00