MerryMage
93fcbdf1e2
A64: Implement FCMP, FCMPE
2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
52268298a8
a64_emit_x64: Perform RSB predictions
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
88ae7fce52
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
Lioncash
7abd673a49
A64: Zero upper 64 bits in ORN if using the 64-bit variant
...
Resolves a TODO
2020-04-22 20:44:38 +01:00
MerryMage
ba3d6da0c8
load_store_register_unprivileged: bug: LDTRSW
2020-04-22 20:44:38 +01:00
MerryMage
75756137c6
A64: Implement CMEQ (register, vector)
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
James Rowe
589ad7232f
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
2020-04-22 20:44:38 +01:00
James Rowe
ae880d8391
A64: Fix bugs and address review comments
2020-04-22 20:44:38 +01:00
James Rowe
3aeb7ca50c
Add missing returns
2020-04-22 20:44:38 +01:00
James Rowe
41e6e659c5
A64: Implement Load/Store register (unprivileged)
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
6033b05ca6
A64: Implement LDR/STR (immediate, SIMD&FP)
2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
3caf192f60
A64: Implement DUP (general)
2020-04-22 20:44:37 +01:00
Lioncash
6f9216d544
A64: Implement RBIT
2020-04-22 20:44:37 +01:00
MerryMage
d4b05b28cf
A64: Implement CLS
...
This is not the cleanest implementation.
2020-04-22 20:42:46 +01:00
MerryMage
b8e26bfdc3
A64: Implement ADDP (vector)
2020-04-22 20:42:46 +01:00
Lioncash
bb1c5bd3b2
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
2020-04-22 20:42:46 +01:00
Lioncash
c1a25bfc2f
A64: Implement MADD and MSUB
2020-04-22 20:42:46 +01:00
Lioncash
b7c5055d42
A64: Implement CLZ
2020-04-22 20:42:46 +01:00
MerryMage
4c4efb2213
data_processing_register: Clean-up
2020-04-22 20:42:46 +01:00
Lioncash
ae5dbcbed6
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
...
Truly the most difficult A64 instructions to implement.
2020-04-22 20:42:46 +01:00
Lioncash
4d8f4aa8af
A64: Implement ASRV, LSLV, LSRV, and RORV
2020-04-22 20:42:46 +01:00
Lioncash
a8a65beb2b
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
Thomas Guillemard
896cf44f96
A64: Implement REV, REV32, and REV16 ( #126 )
2020-04-22 20:42:46 +01:00
MerryMage
144b629d8a
A64: Implement CSEL
2020-04-22 20:42:45 +01:00
MerryMage
19da68568e
A64/translate/branch: bug: Read-after-write error in BLR
2020-04-22 20:42:45 +01:00
MerryMage
9f57283a30
A64: Implement SBFM, BFM, UBFM
2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5
A64: Implement MOVN, MOVZ, MOVK
2020-04-22 20:42:45 +01:00
MerryMage
21fe61eac6
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2020-04-22 20:42:45 +01:00
MerryMage
7c4b70751c
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1
A64/translate: Add TranslateSingleInstruction function
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
a1dfa01515
imm: Suppress MSVC warning C4244: value will never be truncated
2020-04-22 20:42:45 +01:00
MerryMage
26da149639
imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions
2020-04-22 20:42:45 +01:00
MerryMage
b34c6616d4
A64/decoder: Split decoder data from header
2020-04-22 20:42:45 +01:00
MerryMage
595f157e5e
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00