MerryMage
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6a269a6ebd
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IR: Add microinstructions UnsignedSaturation and SignedSaturation
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2016-12-21 19:51:25 +00:00 |
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FernandoS27
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8919265d2c
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Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
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2016-12-20 21:52:38 +00:00 |
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FernandoS27
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3f6ecfe245
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Implemented USAD8 and USADA8
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2016-12-20 21:52:38 +00:00 |
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MerryMage
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96e46ba6b5
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Implement QADD, QSUB, QDADD, QDSUB
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2016-12-15 22:34:29 +00:00 |
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MerryMage
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52e1445f43
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Implement USUB8
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2016-12-05 00:29:15 +00:00 |
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MerryMage
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5c1aab1666
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Implement CLZ
Includes tests
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2016-12-04 22:56:33 +00:00 |
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MerryMage
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1a1646d962
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Implement UADD8
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2016-12-04 20:52:33 +00:00 |
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MerryMage
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7cad6949e7
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IR: Implement new pseudo-operation GetGEFromOp
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2016-12-04 20:52:06 +00:00 |
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MerryMage
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e166965f3e
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Implement VCMP
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2016-12-03 11:41:09 +00:00 |
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Merry
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0ff8c375af
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Implement UHSUB8 and UHSUB16 (#48)
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2016-11-26 18:27:21 +00:00 |
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Merry
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cb17f9a3ed
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Implement SHADD8 and SHADD16 (#47)
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2016-11-26 18:12:29 +00:00 |
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MerryMage
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c0c1bb1094
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Implemented UHADD16
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2016-11-26 11:28:20 +00:00 |
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Sebastian Valle
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4d44474ad4
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Implemented the ARM UHADD8 instruction. (#45)
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
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2016-11-25 20:32:22 +00:00 |
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MerryMage
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b6f7b8babd
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ir: Implement GetGEFlags, SetGEFlags
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2016-11-23 19:44:27 +00:00 |
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MerryMage
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dca3b2f079
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Implement VMRS and VMSR
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2016-08-26 22:47:54 +01:00 |
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MerryMage
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b5a86889cd
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Implement VCVT
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2016-08-23 22:20:04 +01:00 |
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MerryMage
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e164ede4dc
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TranslateArm: Implement MRS, MSR (imm), MSR (reg)
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2016-08-15 11:50:49 +01:00 |
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MerryMage
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960d14d18e
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Optimization: Implement Return Stack Buffer
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2016-08-13 00:10:23 +01:00 |
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bunnei
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8e68e6fdd9
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TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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4b09c0d032
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TranslateArm: Implement QADD8 and UQADD8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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127fbe99cb
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TranslateArm: Implement QSUB8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
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86fe29c6d2
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TranslateArm: Implement UQSUB8.
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2016-08-12 19:00:44 +01:00 |
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MerryMage
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df39308e03
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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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Tillmann Karras
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5d26899ac9
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Add simplified LogicalShiftRight64 IR opcode
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2016-08-08 22:27:05 +01:00 |
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Tillmann Karras
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ccb2aa96a5
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Add support for the APSR.Q flag
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2016-08-08 22:27:04 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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MerryMage
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0f412247ed
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VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
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MerryMage
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3f1345a1a5
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VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
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MerryMage
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12e7f2c359
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VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
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MerryMage
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97b5fa173f
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VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
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MerryMage
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ce6b5f8210
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VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
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Tillmann Karras
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846d07d7b5
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Add Sub64 opcode
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
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MerryMage
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b4aa01ccf4
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Merge remote-tracking branch 'tilkax/master'
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2016-08-05 14:14:06 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
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Tillmann Karras
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3fdc093d10
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Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
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09420d190b
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IR: Implement IR microinstructions ALUWritePC and LoadWritePC
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2016-07-12 10:58:14 +01:00 |
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MerryMage
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1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
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2016-07-11 23:11:05 +01:00 |
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MerryMage
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e7922e4fef
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Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
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2016-07-11 22:43:53 +01:00 |
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MerryMage
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d11df9067d
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Implement thumb1_BIC_reg
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2016-07-10 10:44:45 +08:00 |
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MerryMage
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98a64a92b1
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Implement thumb1_ORR_reg
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2016-07-10 09:06:38 +08:00 |
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MerryMage
|
8145b33882
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Implemented thumb1_ROR_reg
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2016-07-10 08:18:17 +08:00 |
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MerryMage
|
92142d5a22
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Implement thumb1_SUB_reg
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2016-07-08 18:49:30 +08:00 |
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