9 commits

Author	SHA1	Message	Date
MerryMage	97b5fa173f	VFP: Implement VSUB	2016-08-07 01:45:52 +01:00
MerryMage	ce6b5f8210	VFP: Implement VABS	2016-08-07 01:27:18 +01:00
MerryMage	4b31ea25a7	VFP: Implement VADD.{F32,F64}	2016-08-06 20:03:15 +01:00
MerryMage	8ff414ee0e	Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.	2016-08-06 20:03:15 +01:00
bunnei	691e4139fa	arm: Implement B/BL/BX instructions.	2016-08-03 16:49:01 -04:00
Tillmann Karras	fc33f1d374	Implement more instructions ... SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16	2016-08-03 00:47:17 +01:00
Tillmann Karras	30a90295b9	Implement data processing instructions ... ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB, TEQ, TST The code could use some serious deduplication...	2016-08-03 00:47:16 +01:00
MerryMage	a875c0c720	TranslateArm: Stub more ARM instructions	2016-08-02 21:59:33 +01:00
MerryMage	6097a21955	TranslateArm: Reorganisation - Split visitor into multiple .cpp files	2016-08-02 11:54:04 +01:00