mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
573 commits 1 branch 0 tags 34 MiB
Commit graph

107 commits

Author SHA1 Message Date
MerryMage
e3bc7d039f Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC 2017-01-08 14:56:06 +00:00
MerryMage
e9df248d56 decoder_detail: Support const member functions 2016-12-23 11:33:40 +00:00
MerryMage
b1bad4b5cc decoder_detail: static_assert member function is from visitor class 
Improves readability of compiler errors.
 2016-12-23 11:10:02 +00:00
MerryMage
c78f153ddb decoder/arm: Sort decoders according to number of bits in mask 2016-12-22 15:25:38 +00:00
MerryMage
cb38c94b58 decoder/arm: Fix decoding of RFE 2016-12-22 15:25:07 +00:00
MerryMage
7e77ee7fd6 decoder/arm: Fix decoding of MCR2 2016-12-22 15:11:47 +00:00
MerryMage
967f3cf7e1 Implement CPS (Thumb) 
* Since currently only User mode is emulated, CPS is a NOP.
 2016-12-21 22:44:27 +00:00
MerryMage
c764a2b889 Implement MUL (T1) 2016-12-21 22:44:14 +00:00
MerryMage
e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
Mat M
f75acd6cfb decoder: Generify the matcher interface (#33) 
Gets rid of a bit of duplication while remaining compatible
with the current interfaces in place.
 2016-09-17 09:48:18 +01:00
MerryMage
dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
MerryMage
b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
MerryMage
78464a8f01 translate_arm/vfp2: Implement VSTM (A1, A2) 2016-08-23 20:54:38 +01:00
MerryMage
af9a68f0d1 translate_arm/vfp2: Implement VLDM (A1, A2) 2016-08-23 20:07:06 +01:00
MerryMage
8c7a81a308 VPOP and VPUSH are floating-point load-store instructions 2016-08-23 14:26:50 +01:00
MerryMage
2d6a86e43c Remove <cassert> 2016-08-19 01:53:24 +01:00
MerryMage
4acc481463 translate_arm/load_store: Handle unpredictable instructions 
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
 2016-08-19 00:59:02 +01:00
MerryMage
36a916a766 decoder/arm: Correct NOP decoder 2016-08-18 18:20:29 +01:00
MerryMage
e9e7ac6e65 decoder/arm: Correct PLD decoder for v6K 2016-08-18 18:19:34 +01:00
Lioncash
9ed9f4c565 mp: Generalize function information retrieval 
Generalizes MemFnInfo to be compatible with all function types.
Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.
 2016-08-17 10:08:40 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
bunnei
30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
bunnei
8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
d0d51ba346 TranslateArm: Implement STM, STMDA, STMDB, STMIB 2016-08-08 22:49:11 +01:00
MerryMage
85549d7ae2 TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB 2016-08-08 22:26:06 +01:00
MerryMage
3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00
MerryMage
a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage
0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage
cd8e7c0504 VFP: Implement VNEG 2016-08-07 12:04:21 +01:00
MerryMage
da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS 2016-08-07 11:49:06 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
8ff414ee0e Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top. 2016-08-06 20:03:15 +01:00
bunnei
8c2300d477 arm: Implement LDRD reg/imm instructions. 2016-08-05 20:05:02 -04:00
bunnei
ec3a98cf95 arm: Implement LDRH reg/imm instructions. 2016-08-05 20:05:01 -04:00
bunnei
192a0fba7a arm: Implement LDRB reg/imm instructions. 2016-08-05 20:05:00 -04:00
bunnei
dfb318f208 arm: Implement STRD reg/imm instructions. 2016-08-05 20:04:59 -04:00
bunnei
e931dc2496 arm: Implement STRH reg/imm instructions. 2016-08-05 20:04:58 -04:00
bunnei
9f77662b24 arm: Implement STRB reg/imm instructions. 2016-08-05 20:04:57 -04:00
bunnei
caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei
b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
Tillmann Karras
eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
bunnei
691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras
fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras
30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00