MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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e60cea3a54
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Add -pedantic-errors compilation flag
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2016-08-01 19:54:31 +01:00 |
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MerryMage
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cd86ef4236
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Add -DBOOST_POOL_NO_MT as a compiler flag
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2016-07-23 05:37:07 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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98bd7ff6a5
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Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
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2016-07-20 12:08:17 +01:00 |
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Merry
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95316b8443
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Merged in Subv/dynarmic/arm_mem_tests (pull request #4)
Added some fuzz tests for most cases of ARM Load/Store instructions
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2016-07-20 10:19:55 +01:00 |
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MerryMage
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95588d3faa
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Fix Thumb BLX (imm), BL (imm) for negative immediates
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2016-07-18 22:48:23 +01:00 |
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MerryMage
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3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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Subv
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fce8f75077
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Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC.
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2016-07-18 16:13:33 -05:00 |
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Subv
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426ffc9971
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Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
These tests do not test the behavior of writing to the PC.
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2016-07-18 16:13:02 -05:00 |
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Subv
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c330d9e0e3
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Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests.
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2016-07-18 16:10:35 -05:00 |
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MerryMage
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e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
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Subv
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ccc61472b9
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Added format strings for ARM STRBT encodings A1 and A2
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2016-07-18 14:20:58 -05:00 |
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Subv
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8617bf80a1
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Added format strings for ARM LDRBT encodings A1 and A2
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2016-07-18 14:18:39 -05:00 |
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Subv
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5d5ea9325c
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Added format strings for ARM STRT encodings A1 and A2
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2016-07-18 14:05:53 -05:00 |
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MerryMage
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2363759c62
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Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
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2016-07-18 20:05:35 +01:00 |
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MerryMage
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8a310777a1
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backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
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2016-07-18 20:01:48 +01:00 |
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Subv
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77761ba032
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Added the format strings for LDRT encodings A1 and A2.
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2016-07-18 14:01:18 -05:00 |
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MerryMage
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14dcb18bbe
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Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
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2016-07-18 18:48:08 +01:00 |
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MerryMage
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a605a43ef9
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Implement Thumb Instructions: STRH (imm), LDRH (imm)
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2016-07-18 18:28:52 +01:00 |
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MerryMage
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f9755870bb
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Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
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2016-07-18 18:02:02 +01:00 |
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Merry
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3b8790bf29
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Merged in Subv/dynarmic/small_opt (pull request #3)
Pass the current IR::Block by reference to the emitter.
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2016-07-18 17:38:12 +01:00 |
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MerryMage
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dfef65d98f
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Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
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Subv
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703a46ec99
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Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
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2016-07-18 11:27:33 -05:00 |
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MerryMage
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f7e3d7b8d2
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Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
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MerryMage
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9109b226af
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Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
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2016-07-18 11:16:12 +01:00 |
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MerryMage
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c18a3eeab4
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Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
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2016-07-18 10:38:22 +01:00 |
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MerryMage
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bf99ddd065
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Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
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2016-07-18 10:33:52 +01:00 |
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MerryMage
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28a201da16
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Implement Thumb ADR instruction
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2016-07-18 09:25:33 +01:00 |
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Merry
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6708960aeb
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Merged in Subv/dynarmic/rev (pull request #2)
Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 22:13:36 +01:00 |
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Subv
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0cdf5fe751
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Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 14:45:42 -05:00 |
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Merry
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24aa24b1bc
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Merged in Subv/dynarmic (pull request #1)
Implemented ARM CMP (imm) instruction.
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2016-07-17 19:43:49 +01:00 |
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Subv
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7f09510945
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Implemented ARM CMP (imm) instruction.
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2016-07-17 13:29:37 -05:00 |
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MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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866dce0f23
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tests/Thumb: Add revsh (thumb) test
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2016-07-16 19:22:57 +01:00 |
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MerryMage
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22b1bd7cc7
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tests/Skyeye: Fix thumb REVSH translation
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2016-07-16 19:22:09 +01:00 |
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MerryMage
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3ef9da9a92
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Docs: Design documentation
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2016-07-15 16:47:13 +01:00 |
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MerryMage
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4b1c27e64f
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Implement arm_ADC_imm
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2016-07-14 20:02:41 +01:00 |
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MerryMage
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63242924fc
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Implement thumb16_SVC
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2016-07-14 15:01:30 +01:00 |
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MerryMage
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181f78f36e
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Common: Remove src/common/logging/log.*
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2016-07-14 14:55:08 +01:00 |
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MerryMage
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07eaf100ba
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Reorganise src/frontend: Add subdirectories disassembler and translate
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2016-07-14 14:39:43 +01:00 |
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MerryMage
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9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
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672ffb93d0
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frontend/translator: Skeleton for Arm translator
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2016-07-14 13:28:20 +01:00 |
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MerryMage
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7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
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2016-07-14 12:52:53 +01:00 |
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MerryMage
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4ab4ca58f9
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backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
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2016-07-14 09:02:27 +01:00 |
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MerryMage
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08e848044d
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backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
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2016-07-12 16:46:27 +01:00 |
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MerryMage
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619b451902
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clang support
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2016-07-12 14:31:43 +01:00 |
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MerryMage
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8449deb0bc
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MSVC support
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2016-07-12 13:28:09 +01:00 |
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