Lioncash
089096948a
ir: Add opcodes for performing halving adds
2020-04-22 20:46:17 +01:00
Lioncash
3d00dd63b4
emit_x64_vector: Emit VPMINSQ and VPMINUQ for 64-bit vector min operations if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
b97b71b8aa
emit_x64_vector: Emit VPMAXSQ and VPMAXUQ for 64-bit vector max operations if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
033e400df0
emit_x64_vector_floating_point: Deduplicate accurate NaN handling code
...
Allows the code to both be used from the 32 bit and 64 bit operations without duplicating code.
2020-04-22 20:46:17 +01:00
Lioncash
0f067b7330
emit_x64_vector: Emit VPABSQ in EmitVectorAbs() for the 64-bit case if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
d4ee878cbd
emit_x64_vector: Use VPSRAQ in EmitVectorArithmeticShiftRight64() if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
b38dd191bd
disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
...
Mildly reduces the amount of duplicated behavior
2020-04-22 20:46:17 +01:00
Lioncash
51e4f1d9db
emit_x64_vector: Vectorize fallback path of EmitVectorMaxS32()
2020-04-22 20:46:17 +01:00
Lioncash
c692ccdd6d
emit_x64_vector: Vectorize fallback path of EmitVectorMaxS8()
2020-04-22 20:46:17 +01:00
Lioncash
b194313d8c
emit_x64_vector: Vectorize fallback path in EmitVectorMinU32()
2020-04-22 20:46:17 +01:00
Lioncash
7ceda6d919
emit_x64_vector: Vectorize fallback path in EmitVectorMinU16()
2020-04-22 20:46:17 +01:00
Lioncash
cda85a1da0
emit_x64_vector: Vectorize fallback path in EmitVectorMinS32()
2020-04-22 20:46:17 +01:00
Lioncash
6e08eed210
emit_x64_vector: Vectorize fallback path in EmitVectorMinS8()
2020-04-22 20:46:17 +01:00
Lioncash
0fb6dce689
emit_x64_vector: Remove unnecessary if constexpr expression in LogicalVShift
...
This can simply be merged with the previous one.
2020-04-22 20:46:17 +01:00
Lioncash
5b71b1337b
emit_x64_vector: Avoid left shift of negative value in LogicalVShift
...
Now that we handle the signed variants, we also have to be careful about left shifts with negative values,
as this is considered undefined behavior.
2020-04-22 20:46:17 +01:00
Lioncash
9954d28868
a64_jitstate: Zero SP and PC on construction of A64JitState
...
Given we zero out/reset everything else in the struct, do the same for these members to keep initialization consistent
2020-04-22 20:46:17 +01:00
Lioncash
4efbd40ea4
backend_x64/callback: Default virtual destructor in the cpp file
...
Prevents the vtable being generated in each translation unit that includes the header (and silences -Wweak-vtables warnings)
2020-04-22 20:46:17 +01:00
Lioncash
edd0b5c8c7
a32_interface/a64_interface: Change reinterpret_casts to static_casts in GetCurrentBlock thunks
...
It's well-defined to static_cast a void* to its proper type.
2020-04-22 20:46:17 +01:00
Lioncash
e71612d394
A64: Implement SSHL (scalar)
2020-04-22 20:46:17 +01:00
Lioncash
ef1e69a1e3
A64: Implement SSHL (vector)
2020-04-22 20:46:17 +01:00
Lioncash
21974ee57e
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
...
Also adds IR opcodes to dispatch said variants
2020-04-22 20:46:17 +01:00
Lioncash
9fc89f0a0e
emit_x64_vector_floating_point: Use arrays for retrieving size instead of hardcoding the size
...
Similar changes were done in emit_x64_vector, but these were missed.
2020-04-22 20:46:17 +01:00
Lioncash
af28e89a13
emit_x64_vector: Vectorize fallback path in EmitVectorMaxU16()
2020-04-22 20:46:17 +01:00
Lioncash
cda75e2079
A64: Implement CMTST's scalar variant
2020-04-22 20:46:17 +01:00
Lioncash
0d20423ad5
emit_x64_vector: Vectorize non-SSE4.1 fallback path for VectorMultiply32()
2020-04-22 20:46:17 +01:00
Lioncash
d70ee7c0d1
emit_x64_vector: Use VBPROADCAST where applicable and available
...
Uses the instruction that does what it says in its name if available. Allows avoiding the use
of a scratch register in EmitVectorBroadcast8() and EmitVectorBroadcastLower8()'s SSSE3 path.
2020-04-22 20:46:17 +01:00
Lioncash
bebe7235ae
A64: Implement UZP1 and UZP2
2020-04-22 20:46:17 +01:00
Lioncash
26d77c6f09
ir: Add opcodes for performing vector deinterleaving
2020-04-22 20:46:17 +01:00
Lioncash
d6f9ed47d9
A64: Implement FNEG (half-precision)
2020-04-22 20:46:17 +01:00
Lioncash
7efbd73bac
A64: Implement USHL (scalar)
2020-04-22 20:46:17 +01:00
Lioncash
41f4717f2b
A64: Implement FNEG (vector)
2020-04-22 20:46:17 +01:00
Lioncash
ba1cc6366d
A64: Implement RSUBHN/RSUBHN2
2020-04-22 20:46:17 +01:00
Lioncash
e41640fe33
A64: Implement RADDHN/RADDHN2
2020-04-22 20:46:17 +01:00
Lioncash
b719a6b3f7
A64: Implement XAR
2020-04-22 20:46:17 +01:00
Lioncash
0b1b131ec2
simd_two_register_misc: Factor out common comparison code
...
Gets rid of a tiny bit of duplicated code.
2020-04-22 20:46:17 +01:00
Lioncash
ed0b84da70
A64: Implement CMLE (zero)'s vector variant
2020-04-22 20:46:17 +01:00
Lioncash
b595a68ffa
A64: Implement CMTST (vector)
2020-04-22 20:46:17 +01:00
Lioncash
48c7f8630c
A64: Implement ADDHN{2} and SUBHN{2}
2020-04-22 20:46:17 +01:00
Lioncash
3acd9c9200
translate: zero extend result in Vpart when storing to lower part of vector
2020-04-22 20:46:17 +01:00
Lioncash
87ca63699f
emit_x64_vector: Emit PMAXUD in EmitVectorMaxU32 on SSE4.1-capable CPUs
2020-04-22 20:46:17 +01:00
Lioncash
f17702f608
emit_x64_vector: Emit PMINUD in EmitVectorMinU32 on SSE4.1-capable CPUs
2020-04-22 20:46:17 +01:00
Lioncash
596a8dd1dd
emit_x64_vector: Emit PMINSD in EmitVectorMinS32 on SSE4.1-capable CPUs
...
Provides a better alternative to a fallback operation.
2020-04-22 20:46:17 +01:00
Lioncash
75fd4eaaaa
emit_x64_vector: Get rid of some magic numbers in loop bounds
2020-04-22 20:46:17 +01:00
Lioncash
7b80ac25eb
emit_x64_vector: Generify variable shift functions
2020-04-22 20:46:17 +01:00
Lioncash
4ec735f707
A64: Implement CMLE (zero)'s scalar variant
2020-04-22 20:46:17 +01:00
Lioncash
6534184df2
A64: Implement CMLT (zero)'s scalar single/double-precision variant
2020-04-22 20:46:17 +01:00
Lioncash
8863c9bb4b
A64: Implement SHA512H2
2020-04-22 20:46:17 +01:00
Lioncash
033b890e25
A64: Implement SHA512H
2020-04-22 20:46:17 +01:00
Lioncash
d1f5b084b4
A64: Handle S32->F32 case for SCVTF (vector)
2020-04-22 20:46:17 +01:00
Lioncash
38fa984b53
IR: Add opcode for packed word->f32 conversions
2020-04-22 20:46:16 +01:00
Lioncash
b8587d8e34
A64: Implement SHA512SU1
2020-04-22 20:46:16 +01:00
Lioncash
44d846045a
A64: Implement SHA512SU0
2020-04-22 20:46:16 +01:00
Lioncash
ca903c1585
A64: Implement SHA256H and SHA256H2
2020-04-22 20:46:16 +01:00
MerryMage
e4237c44eb
A64: Implement SCVTF (vector, integer), scalar varaint
2020-04-22 20:46:16 +01:00
MerryMage
bfba38d0b6
impl: Reorganize scalar two-register misc instructions
2020-04-22 20:46:16 +01:00
Lioncash
ea582b17cc
A64: Implement SHA256SU1
2020-04-22 20:46:16 +01:00
Lioncash
06c5dcaf5e
simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
2020-04-22 20:46:16 +01:00
Lioncash
0d50d7314b
A64: Implement CMGE (zero)'s vector variant
2020-04-22 20:46:16 +01:00
Lioncash
ab35dc0e78
A64: Implement MLS (by element)
2020-04-22 20:46:16 +01:00
Lioncash
1651e60462
A64: Implement MUL (by element)
2020-04-22 20:46:16 +01:00
MerryMage
a86d4093cd
A64: Implement MLA (by element)
2020-04-22 20:46:16 +01:00
Lioncash
7f47402609
A64: Implement ABS (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
c8eb4528be
A64: Implement SHA256SU0
2020-04-22 20:46:16 +01:00
Lioncash
181c3b0790
A64: Implement SHA1M
2020-04-22 20:46:16 +01:00
Lioncash
47bc97a71b
A64: Implement SHA1P
2020-04-22 20:46:16 +01:00
Lioncash
718f3e9bb4
A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions
...
These can trivially use the ScalarCompare helper function.
2020-04-22 20:46:16 +01:00
Lioncash
3ad4e547e4
A64: Implement scalar variant of NEG
2020-04-22 20:46:16 +01:00
Lioncash
b4f3051e4b
simd: Relocate REV16, REV32 and REV64 vector variants to the proper file
...
These aren't scalar instruction variants.
2020-04-22 20:46:16 +01:00
Lioncash
19e276d10f
A64: Implement CMEQ (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
5b8c9e5146
A64: Implement CMHS (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
78bb12276a
A64: Implement CMHI (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
c18b20b8d1
A64: Implement CMGE (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
755981d0da
A64: Implement CMGT (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
da6627124b
A64: Implement SHA1C
2020-04-22 20:46:16 +01:00
Lioncash
3c013bd9f8
A64: Implement SLI (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
154cac594a
A64: Implement SRI (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
6bcfdba1ad
general: Remove unused lambda captures
...
Resolves warnings that occur in Xcode 9.3
2020-04-22 20:46:16 +01:00
Lioncash
205ca6b4cb
A64: Implement SHA1SU1
2020-04-22 20:46:16 +01:00
Lioncash
16a001b9ff
A64: Implement SHA1SU0
2020-04-22 20:46:16 +01:00
Lioncash
3b6db59850
A64: Implement TRN2
2020-04-22 20:46:16 +01:00
Lioncash
30e158f8d0
A64: Implement TRN1
2020-04-22 20:46:16 +01:00
Lioncash
52cad2d9d0
A64: Implement SSRA (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
255a33936d
A64: Implement SSHR (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
6723b00497
A64: Implement USRA (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
d56fa8f735
A64: Implement USHR (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
870e418b0b
A64: Implement SHL (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
97f2bea4f2
A64: Implement SM3PARTW1
2020-04-22 20:46:16 +01:00
Lioncash
e268b110f0
simd_sha512: Simplify RAX1
...
Now that the vector rotation helpers are in, replace the explicit
shifting with the relevant helper function that does the same thing.
Simply tidies up code; no behavioral changes are made.
2020-04-22 20:46:16 +01:00
Lioncash
20d2491267
A64: Implement SM3PARTW2
2020-04-22 20:46:16 +01:00
Lioncash
e1b662e90c
ir: Add helper functions for vector rotation
2020-04-22 20:46:16 +01:00
Lioncash
8a60a63a8b
A64: Implement SM3TT2B
2020-04-22 20:46:16 +01:00
Lioncash
b3d4c02098
A64: Implement SM3TT2A
2020-04-22 20:46:16 +01:00
Lioncash
7fbccabd81
A64: Implement SM3TT1B
2020-04-22 20:46:16 +01:00
Lioncash
769373b3ed
A64: Implement SM3TT1A
2020-04-22 20:46:16 +01:00
Lioncash
2d269fdcc7
simd_shift_by_immediate: Merge signed/unsigned helper functions
...
Gets rid of a little more code duplication.
2020-04-22 20:46:16 +01:00
Lioncash
d5461be6b4
A64: Implement SM3SS1
2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83
A64: Implement SRI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26
A64: Implement SLI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7
A64: Implement SRSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7
A64: Implement SRSHR (vector)
2020-04-22 20:46:16 +01:00
MerryMage
6c9c829a08
imm: Add additional bit position checks to Imm::Bits
2020-04-22 20:46:16 +01:00
MerryMage
be907a61f7
math_util: rvalue references for std::forward
2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3
A64: Implement SSUBL/SSUBL2
2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8
A64: Implement SADDL/SADDL2
2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d
A64: Implement USUBL/USUBL2
2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a
A64: Implement UADDL/UADDL2
2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f
simd_shift_by_immediate: Factor out common code in shift instructions
...
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.
e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
2020-04-22 20:46:16 +01:00
Lioncash
56803f5203
A64: Implement URSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d
A64: Implement URSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
16613ee066
A64: Implement RSHRN/RSHRN2
2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a
A64: Implement SHRN/SHRN2
2020-04-22 20:46:15 +01:00
Lioncash
80e005e5b5
A64/translate: Amend I() to also handle u8 and u16 immediates
...
This is necessary for instructions like SRSHR, and other related instructions.
2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3
A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0
A64: Implement ZIP2
2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0
decoder/a64: Tweak ordering algorithm
...
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
2020-04-22 20:46:15 +01:00
MerryMage
575590d18d
ir_emitter: Remove overloads
...
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1
A64: Implement RBIT (vector)
2020-04-22 20:46:15 +01:00
Lioncash
64b1f2d468
ir: Add opcode for reversing bits in a vector
2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb
A64/translate: Amend instruction prototypes erroneously marked as taking Reg
...
Makes the prototypes consistent
2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3
A64: Implement RAX1
2020-04-22 20:46:15 +01:00
Lioncash
7371e63a7b
a64_get_set_elimination_pass: Make TrackingType enum an enum class
...
Prevents placing single letter enum members into the surrounding scope.
2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a
A64: Implement ABS (vector)
2020-04-22 20:46:15 +01:00
Lioncash
e33dcce14a
ir: Add opcodes for performing vector absolute values
2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9
A64: Implement USUBW/USUBW2
2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a
A64: Implement SSUBW/SSUBW2
2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9
A64: Implement SADDW/SADDW2
2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9
A64: Implement EXT
2020-04-22 20:46:15 +01:00
MerryMage
3472f371df
IR: Implement VectorExtract, VectorExtractLower IR instructions
2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e
A64: Implement UADDW
2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888
A64: Implement FMUL (vector)
2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd
A64: Implement UABA
...
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e
A64: Implement UABD
2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce
ir: Add opcodes for performing vector unsigned absolute differences
2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3
ir_emitter: Make immediate member functions const qualified
...
These don't modify class state
2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e
IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords
...
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b
A64: Implement SHA1H
...
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
2020-04-22 20:46:15 +01:00
Lioncash
3985f7bf84
emit_x64_data_processing: Deduplicate some code in zero-extension functions
...
EmitZeroExtendByteToLong() can be implemented in terms of EmitZeroExtendByteToWord() and
EmitZeroExtendHalfToLong() can be implemented in terms of EmitZeroExtendHalfToWord().
2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b
A64: NOP immediate variant of PRFM
...
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
2020-04-22 20:46:15 +01:00
MerryMage
e7b60189b3
abi: Missing includes'
2020-04-22 20:46:15 +01:00
MerryMage
cdc5c3ad95
emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64}
2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276
A64: system: Use an enum class for MRS/MSR register encodings
...
Reduces the need to manually write out the register bit encodings repeatedly.
2020-04-22 20:46:15 +01:00
MerryMage
df4ee0f51e
emit_X64_floating_point: Near jmp to end instead of short jmp
...
Jump destination can be further than what can be reached in a short
jump under some FPCR options.
2020-04-22 20:46:15 +01:00
Lioncash
b8d5765f9b
emit_x64_vector: Fix typo in VectorShuffleImpl
...
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d
A64: Implement REV64
2020-04-22 20:46:15 +01:00
Lioncash
ade595e377
bit_util: Do nothing in RotateRight if the rotation amount is zero
...
Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.
We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3
A64: Implement REV32 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6b0010c940
ir: Add IR opcodes for emitting vector shuffles
...
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2020-04-22 20:46:15 +01:00
Lioncash
eb2d28d2b1
emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0
A64: Implement REV16 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6177c2c63d
CMakeLists: Add fp_util, macro_util and math_util headers
...
Allows the headers to show up within IDEs
2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a
A64: Implement EOR3 and BCAX
2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2
impl: Update PC when raising exception
2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad
A64: Implement FDIV (vector)
2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68
system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d
Correct FPSR and FPCR
2020-04-22 20:46:15 +01:00
MerryMage
147284427b
A64: Implement USHL
2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195
A64: Implement UCVTF (vector, integer), scalar variant
2020-04-22 20:46:15 +01:00
MerryMage
be57608353
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676
A64: Implement system register TPIDR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e
A64: Implement system registers FPCR and FPSR
2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d
A64: Implement system register CNTPCT_EL0
2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00
A64: Implement system register CTR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b
A64: Implement NEG (vector)
2020-04-22 20:46:15 +01:00
MerryMage
710d09471b
IR: Add IR instruction ZeroVector
2020-04-22 20:46:15 +01:00
MerryMage
2721bb5ace
emit_x64_floating_point: Add maybe_unused to preprocess parameter
2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b
A64: Implement FMINNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07
A64: Implement FMAXNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
1dfce0894d
constant_pool: Add frame parameter
2020-04-22 20:46:14 +01:00
MerryMage
bd2b415850
A64: Implement ADDP (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
84f1c9b7f4
reg_alloc: Only exchange GPRs
2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0
A64: Implement DUP (element), scalar variant
2020-04-22 20:46:14 +01:00
MerryMage
6541ec064d
emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41
A64: Implement FMAX (scalar), FMIN (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
7c193485e1
a64/config: Allow NaN emulation accuracy to be set
2020-04-22 20:46:14 +01:00
MerryMage
a3df46a75a
a64_emit_x64: Add conf to A64EmitContext
2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198
A64: Implement FSQRT (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
07520f32c3
backend_x64: Accurately handle NaNs
2020-04-22 20:46:14 +01:00
MerryMage
e97581d063
fuzz_with_unicorn: Print AArch64 disassembly
2020-04-22 20:46:14 +01:00
MerryMage
01c1e9017e
T32: Add initial decoder list
2020-04-22 20:46:14 +01:00
MerryMage
ccf7df057b
simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab
decoder/a64: Rearrange SIMD two-register misc decoders
2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06
A64: Implement CMGE (register)
2020-04-22 20:46:14 +01:00
MerryMage
9d85991906
A64: Implement CMHI, CMHS
2020-04-22 20:46:14 +01:00
MerryMage
e2b9b7c5b0
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73
A64: Implement SMAX, SMIN, UMAX, UMIN
2020-04-22 20:46:14 +01:00
MerryMage
47c0ad0fc8
IR: Implement Vector{Max,Min}{Signed,Unsigned}
2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f
A64: Implement CMGT (register)
2020-04-22 20:46:14 +01:00
MerryMage
f4775910f5
IR: Implement VectorGreaterSigned
2020-04-22 20:46:14 +01:00
MerryMage
1f5b3bca43
Exclusive fixups
...
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
2020-04-22 20:46:14 +01:00
MerryMage
f3fa4a042f
a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
2020-04-22 20:46:14 +01:00
MerryMage
8698f057d0
A64: Implement STXP, STLXP, LDXP, LDAXP
2020-04-22 20:46:14 +01:00
MerryMage
2a6619d59c
A64: Implement CLREX
2020-04-22 20:46:14 +01:00
MerryMage
b7a2c1a7df
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2020-04-22 20:46:14 +01:00
MerryMage
a6cc667509
Direct Page Table Access: Handle address spaces less than the full 64-bit in size
2020-04-22 20:46:14 +01:00
MerryMage
f45a5e17c6
Implement direct page table access
2020-04-22 20:46:14 +01:00
MerryMage
bfd3e30c75
callbacks: Member functions should be const
2020-04-22 20:46:14 +01:00
MerryMage
9f2f08db8d
a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
2020-04-22 20:46:14 +01:00
MerryMage
6c4773e85b
abi: Add RAX to ABI_ALL_CALLER_SAVE
2020-04-22 20:46:14 +01:00
MerryMage
8756487554
A64: Partially implement MRS
2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe
A64: Implement DSB, DMB
2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d
Implement DC instructions
2020-04-22 20:46:14 +01:00
Lioncash
a9153218bd
A64: Implement NOT (vector)
2020-04-22 20:46:14 +01:00
MerryMage
2cb0a699ba
IR: Implement FPMax, FPMin
2020-04-22 20:46:14 +01:00
MerryMage
aed4fd3ec3
A64: Implement FADD (vector), vector variant
2020-04-22 20:46:14 +01:00
MerryMage
98c8e7d1af
IR: Implement FPVectorAdd
2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee
A64: Implement SSHLL, SSHLL2
2020-04-22 20:46:14 +01:00
MerryMage
eae518a338
IR: Implement VectorSignExtend
2020-04-22 20:46:14 +01:00
MerryMage
3738043e58
A64: Implement DUP (element), vector variant
2020-04-22 20:46:14 +01:00
MerryMage
ce7628b6b5
load_store_multiple_structures: Improve IR codegen for selem == 1 case
2020-04-22 20:46:14 +01:00
MerryMage
f1cb5581c9
A64: Implement FSUB (vector)
2020-04-22 20:46:14 +01:00
MerryMage
b9cd345ddc
IR: Implement FPVectorSub
2020-04-22 20:46:14 +01:00
MerryMage
851fc83445
emit_x64_vector: EmitOneArgumentFallback
2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b
Forward declare IR::Opcode and IR::Type where possible
2020-04-22 20:46:14 +01:00
MerryMage
6c9b4f0114
A64: Implement CNT
2020-04-22 20:46:14 +01:00
MerryMage
303088a51e
IR: Implement VectorPopulationCount
2020-04-22 20:46:14 +01:00
MerryMage
1dd2b33b87
A64: Implement MLS (vector)
2020-04-22 20:46:14 +01:00
MerryMage
5eac3abf52
A64: Implement MLA (vector)
2020-04-22 20:46:14 +01:00
MerryMage
bf2cd92da9
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
2020-04-22 20:46:14 +01:00
MerryMage
b062266b8e
emit_x64_vector: More explicit lambda decay
2020-04-22 20:46:14 +01:00
MerryMage
3afd2fcbad
A64: Implement MUL (vector)
2020-04-22 20:46:14 +01:00
MerryMage
b6de612e01
IR: Implement VectorMultiply
2020-04-22 20:46:14 +01:00
MerryMage
90a053a5e4
emit_x64_vector: Order alphabetically
2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
2020-04-22 20:46:14 +01:00
MerryMage
a455ff70c9
decoder/a64: Don't rearrange unrelated decoders
2020-04-22 20:46:14 +01:00
MerryMage
faeb77e8c4
A64: Implement SUB (vector)
2020-04-22 20:46:14 +01:00
MerryMage
bd106c3ae7
A64: Implement SIMD instruction SSRA, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
f58aba9871
A64: Implement SIMD instruction SSHR, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
715ae1c229
IR: Implement VectorArithmeticShiftRight
2020-04-22 20:46:14 +01:00
MerryMage
653c82d8f0
impl: Improve Vpart setter
2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35
A64: Implement SIMD instructions XTN, XTN2
2020-04-22 20:46:13 +01:00
MerryMage
132c783320
IR: Implement VectorNarrow
2020-04-22 20:46:13 +01:00
MerryMage
1423584f9f
constant_pool: Allow for 128-bit constants
2020-04-22 20:46:13 +01:00
MerryMage
69de50a878
emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
2020-04-22 20:46:13 +01:00
MerryMage
cbc9f361b0
IR: Implement VectorSub
2020-04-22 20:46:13 +01:00
MerryMage
3f93c77ace
A64: Implement SIMD instruction USRA, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
fb9d20f27f
A64: Implement SIMD instruction USHR, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
b22c5961f9
IR: Implement VectorLogicalShiftRight
2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b
A64: Implement SIMD instructions USHLL, USHLL2
2020-04-22 20:46:13 +01:00
MerryMage
59ace60b03
IR: Implement VectorZeroExtend
2020-04-22 20:46:13 +01:00
MerryMage
d3a4e1efe2
IR: Vector instructions now take esize argument in emitter
2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23
A64: Implement SIMD instruction SHL
2020-04-22 20:46:13 +01:00
MerryMage
f6247125c0
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2020-04-22 20:46:13 +01:00
MerryMage
15e8231f24
opcodes: Sort vector IR opcodes alphabetically
2020-04-22 20:46:13 +01:00
MerryMage
d74f4e35f6
block_of_code: Increase constant pool size
2020-04-22 20:46:13 +01:00
MerryMage
e69288f803
devirtualize: MinGW uses Intanium MFP ABI
2020-04-22 20:46:13 +01:00
MerryMage
ad428cbd7a
callback: Properly handle calls with return pointers and simplify interface
2020-04-22 20:46:13 +01:00
FernandoS27
15871910af
Implemented BSL, BIC, BIT and BIF vector instructions
2020-04-22 20:46:13 +01:00
MerryMage
7a87e3fc55
devirtualize: Handle Windows ABI
2020-04-22 20:46:13 +01:00
MerryMage
ba4a779c62
A32/decoder/arm: bug: Correct bitstring for SRS
2020-04-22 20:46:13 +01:00
MerryMage
f808a0fbde
devirtualize: Devirtualize Itanium ABI MFPs at runtime
2020-04-22 20:46:13 +01:00
MerryMage
afe16fa0f3
cast_util: Add BitCast and BitCastPointee
2020-04-22 20:46:13 +01:00
Lioncash
4e33629b0e
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
2020-04-22 20:46:13 +01:00
Lioncash
35a29a9665
A64: Implement ZIP1
2020-04-22 20:46:13 +01:00
FernandoS27
586854117b
Implemented UMULH and SMULH instructions
2020-04-22 20:46:13 +01:00
MerryMage
1a7b7b541a
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
...
There wasn't a clean way to seperate these instructions out.
2020-04-22 20:46:13 +01:00
MerryMage
8ab7d8175c
impl: Add AdvSIMDExpandImm
2020-04-22 20:46:13 +01:00
MerryMage
ea69cb4474
A64: Implement SUB (vector), scalar variant
2020-04-22 20:46:13 +01:00
MerryMage
4c5871d5d5
A64: Implement ADD (vector), scalar variant
2020-04-22 20:46:13 +01:00
MerryMage
2a0850c068
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
2020-04-22 20:46:13 +01:00
MerryMage
7b33772ac6
A64: Implement BIC (vector, register)
2020-04-22 20:46:13 +01:00
MerryMage
eb5591859c
A64: Implement FMOV (general)
2020-04-22 20:46:13 +01:00
MerryMage
dd88cee15a
translate/impl: Add Vpart
2020-04-22 20:46:13 +01:00
MerryMage
cc9efd13c9
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
2020-04-22 20:46:13 +01:00
MerryMage
81713c2b77
A64: Implement FCCMPE
2020-04-22 20:46:13 +01:00
MerryMage
ef906dbbfa
A64: Implement FCCMP
2020-04-22 20:46:13 +01:00
MerryMage
44c3c2312a
a64_jitstate: Remove unnecessary FPSCR_nzcv member
2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
Lioncash
2ee39d6b36
A64: Implement FMOV (register)
2020-04-22 20:46:13 +01:00
MerryMage
b02b861242
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
2020-04-22 20:46:13 +01:00
Lioncash
5a65313236
A64: Implement CCMP (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
ab4664de61
A64: Implement CCMN (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
a6c6539109
A64: Implement CCMP (register)
2020-04-22 20:46:13 +01:00
Lioncash
22632db337
microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
2020-04-22 20:46:13 +01:00
MerryMage
c5033b5dda
A64: Implement CCMN (register)
2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe
IR: Add ConditionalSelectNZCV instruction
2020-04-22 20:46:13 +01:00
MerryMage
4491746eae
A64: Implement FNEG
2020-04-22 20:46:13 +01:00
MerryMage
db958061a3
A64: Implement FABS
2020-04-22 20:46:13 +01:00
MerryMage
8765b421b7
A64: Implement FCSEL
2020-04-22 20:46:13 +01:00
MerryMage
7e82d8eede
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
2409e5d082
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
b173fcf34e
backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
...
They're inaccurate in terms of FPSR at the moment anyway.
2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
2020-04-22 20:46:13 +01:00
Lioncash
d040920727
Common: Put AES code within its own nested namespace
...
Prevents the functions from potentially clashing with other stuff in Common in the future
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7
A64: Implement AESD
2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7
A64: Implement AESE
2020-04-22 20:46:13 +01:00
MerryMage
68f46c8334
backend_x64: Use a reference to BlockOfCode instead of a pointer
2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
0bb4474fb9
A64: Implement INS (general)
2020-04-22 20:46:13 +01:00
MerryMage
d13704fdef
A64: Implement INS (element)
2020-04-22 20:46:13 +01:00
MerryMage
0642d49919
A64: Implement SMOV
2020-04-22 20:46:13 +01:00
MerryMage
5297027ebe
A64: Implement UMOV
2020-04-22 20:46:13 +01:00
MerryMage
47661b746b
basic_block: Fix bogus GCC maybe-uninitialized warning
2020-04-22 20:46:13 +01:00
MerryMage
1fb0957aa3
A64: Implement FCVT
2020-04-22 20:46:13 +01:00
MerryMage
ca38225e08
fuzz_with_unicorn: Skip instructions that need to be interpreted
2020-04-22 20:46:13 +01:00
MerryMage
4be55b8b84
A64: Implement FMOV (scalar, immediate)
2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2
A64: Implement FCMP, FCMPE
2020-04-22 20:46:13 +01:00
MerryMage
75b8a76630
a64_jitstate: A64 does not have a seperate FPSCR.NZCV
2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
2020-04-22 20:46:13 +01:00
MerryMage
429dc24587
IR: Merge U32 and U64 variants of FP instructions
2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2020-04-22 20:46:13 +01:00
MerryMage
6414736a8d
emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
...
This bug wasn't discovered earlier because we previously only used index == 0.
2020-04-22 20:46:13 +01:00
MerryMage
ebfc51c609
IR: Implement VectorSetElement{8,16,32,64}
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
744495e23d
iterator_util: Make Reverse constexpr
...
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
2020-04-22 20:46:12 +01:00
Lioncash
ab9b5fb8aa
Common: Relocate common bits of CRC32
...
Allows the algorithm to be used in any other potential backend.
2020-04-22 20:46:12 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
MerryMage
64761dbc72
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
2020-04-22 20:46:12 +01:00
MerryMage
bafb39ebc5
A64: Add Disassemble method
2020-04-22 20:46:12 +01:00
MerryMage
cc0eb18a0b
A32: data_processing: Remove !S assertions
2020-04-22 20:46:12 +01:00
MerryMage
865a30eb0d
A32: Implement BKPT
2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
52268298a8
a64_emit_x64: Perform RSB predictions
2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90
A32: Change UserCallbacks to be similar to A64's interface
2020-04-22 20:46:12 +01:00
Lioncash
b9ce660113
reg_alloc: std::move RegAlloc's function argument
2020-04-22 20:46:12 +01:00
Lioncash
ed561d6653
General: Add missing override specifiers
2020-04-22 20:46:12 +01:00
MerryMage
b2d99eddc6
EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
2020-04-22 20:46:12 +01:00
MerryMage
f4f774f9f6
a64_get_set_elimination_pass: Simplify algorithm
2020-04-22 20:46:12 +01:00
MerryMage
54de64f5bf
a64_emit_x64: bug: x64 sign-extends 32-bit immediates
2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd
ir_opt: Add A64 Get/Set Elimination Pass
2020-04-22 20:46:12 +01:00
MerryMage
e01b500aea
ir_emitter: Allow the insertion point for new instructions to be set
2020-04-22 20:46:12 +01:00
MerryMage
af793c2527
{a32,a64}_interface: Predict entrypoint
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
88ae7fce52
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
2020-04-22 20:44:38 +01:00
MerryMage
d497464c9f
a64_jitstate: Have 128-bit wide spills
2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
MerryMage
16fa2cd8f6
a64_emit_x64: Use xword from Xbyak::util
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
Lioncash
7abd673a49
A64: Zero upper 64 bits in ORN if using the 64-bit variant
...
Resolves a TODO
2020-04-22 20:44:38 +01:00
MerryMage
ba3d6da0c8
load_store_register_unprivileged: bug: LDTRSW
2020-04-22 20:44:38 +01:00
MerryMage
75756137c6
A64: Implement CMEQ (register, vector)
2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2020-04-22 20:44:38 +01:00
MerryMage
4ce9c65cfb
reg_alloc: Use std::exchange
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
MerryMage
94383fd934
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
2020-04-22 20:44:38 +01:00
MerryMage
d124a1d761
emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
...
For CPUs that didn't support SSE4.1, this was a bug.
2020-04-22 20:44:38 +01:00
James Rowe
589ad7232f
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
2020-04-22 20:44:38 +01:00
James Rowe
ae880d8391
A64: Fix bugs and address review comments
2020-04-22 20:44:38 +01:00
James Rowe
3aeb7ca50c
Add missing returns
2020-04-22 20:44:38 +01:00
James Rowe
41e6e659c5
A64: Implement Load/Store register (unprivileged)
2020-04-22 20:44:37 +01:00
MerryMage
01a26fa644
fixup: travis: Test with disabled CPU feature detection
2020-04-22 20:44:37 +01:00
Lioncash
5281d3c6d5
CMakeLists: Add opcodes.inc to the source file list
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Allows the file to show up nicely within IDEs
2020-04-22 20:44:37 +01:00
MerryMage
30936f5e94
travis: Test with disabled CPU feature detection
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Ensure that fallbacks are working correctly.
2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30
IR: Add IR instruction VectorZeroUpper
2020-04-22 20:44:37 +01:00
MerryMage
da3e9a5704
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
6033b05ca6
A64: Implement LDR/STR (immediate, SIMD&FP)
2020-04-22 20:44:37 +01:00