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54 commits

Author SHA1 Message Date
MerryMage
cd8e7c0504 VFP: Implement VNEG 2016-08-07 12:04:21 +01:00
MerryMage
da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS 2016-08-07 11:49:06 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
c35f06470f VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1 2016-08-06 23:01:18 +01:00
MerryMage
94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras
55204a80d0 Implement SMMLA, SMMLS, SMMUL 2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
MerryMage
7915f97d98 TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning) 2016-08-06 20:42:06 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
8ff414ee0e Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top. 2016-08-06 20:03:15 +01:00
bunnei
2448d52394 load_store: Use correct types for LDR/STR. 2016-08-05 20:51:32 -04:00
bunnei
8c2300d477 arm: Implement LDRD reg/imm instructions. 2016-08-05 20:05:02 -04:00
bunnei
72608b7af6 arm: Handle Cond::NV (some 3DS games use this despite being obsolete). 2016-08-05 20:05:02 -04:00
bunnei
ec3a98cf95 arm: Implement LDRH reg/imm instructions. 2016-08-05 20:05:01 -04:00
bunnei
192a0fba7a arm: Implement LDRB reg/imm instructions. 2016-08-05 20:05:00 -04:00
bunnei
dfb318f208 arm: Implement STRD reg/imm instructions. 2016-08-05 20:04:59 -04:00
bunnei
e931dc2496 arm: Implement STRH reg/imm instructions. 2016-08-05 20:04:58 -04:00
bunnei
9f77662b24 arm: Implement STRB reg/imm instructions. 2016-08-05 20:04:57 -04:00
bunnei
caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei
b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
Tillmann Karras
fce8c86c90 Implement RSB 
somehow missed this earlier
 2016-08-05 02:13:26 +01:00
Tillmann Karras
eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
bunnei
691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras
fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras
30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
MerryMage
a875c0c720 TranslateArm: Stub more ARM instructions 2016-08-02 21:59:33 +01:00
MerryMage
6097a21955 TranslateArm: Reorganisation - Split visitor into multiple .cpp files 2016-08-02 11:54:04 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage
2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
MerryMage
14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) 2016-07-18 18:48:08 +01:00
MerryMage
a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) 2016-07-18 18:28:52 +01:00
MerryMage
f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) 2016-07-18 18:02:02 +01:00
MerryMage
dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) 2016-07-18 11:16:12 +01:00
MerryMage
c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage
bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic 2016-07-18 10:33:52 +01:00
MerryMage
28a201da16 Implement Thumb ADR instruction 2016-07-18 09:25:33 +01:00
Subv
0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
Merry
24aa24b1bc Merged in Subv/dynarmic (pull request #1) 
Implemented ARM CMP (imm) instruction.
 2016-07-17 19:43:49 +01:00
Subv
7f09510945 Implemented ARM CMP (imm) instruction. 2016-07-17 13:29:37 -05:00