MerryMage
44c3c2312a
a64_jitstate: Remove unnecessary FPSCR_nzcv member
2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe
IR: Add ConditionalSelectNZCV instruction
2020-04-22 20:46:13 +01:00
MerryMage
b173fcf34e
backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
...
They're inaccurate in terms of FPSR at the moment anyway.
2020-04-22 20:46:13 +01:00
Lioncash
d040920727
Common: Put AES code within its own nested namespace
...
Prevents the functions from potentially clashing with other stuff in Common in the future
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7
A64: Implement AESD
2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7
A64: Implement AESE
2020-04-22 20:46:13 +01:00
MerryMage
68f46c8334
backend_x64: Use a reference to BlockOfCode instead of a pointer
2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
75b8a76630
a64_jitstate: A64 does not have a seperate FPSCR.NZCV
2020-04-22 20:46:13 +01:00
MerryMage
6414736a8d
emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
...
This bug wasn't discovered earlier because we previously only used index == 0.
2020-04-22 20:46:13 +01:00
MerryMage
ebfc51c609
IR: Implement VectorSetElement{8,16,32,64}
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
ab9b5fb8aa
Common: Relocate common bits of CRC32
...
Allows the algorithm to be used in any other potential backend.
2020-04-22 20:46:12 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
MerryMage
64761dbc72
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
2020-04-22 20:46:12 +01:00
MerryMage
bafb39ebc5
A64: Add Disassemble method
2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
52268298a8
a64_emit_x64: Perform RSB predictions
2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90
A32: Change UserCallbacks to be similar to A64's interface
2020-04-22 20:46:12 +01:00
Lioncash
b9ce660113
reg_alloc: std::move RegAlloc's function argument
2020-04-22 20:46:12 +01:00
Lioncash
ed561d6653
General: Add missing override specifiers
2020-04-22 20:46:12 +01:00
MerryMage
b2d99eddc6
EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
2020-04-22 20:46:12 +01:00
MerryMage
54de64f5bf
a64_emit_x64: bug: x64 sign-extends 32-bit immediates
2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd
ir_opt: Add A64 Get/Set Elimination Pass
2020-04-22 20:46:12 +01:00
MerryMage
af793c2527
{a32,a64}_interface: Predict entrypoint
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
d497464c9f
a64_jitstate: Have 128-bit wide spills
2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
MerryMage
16fa2cd8f6
a64_emit_x64: Use xword from Xbyak::util
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2020-04-22 20:44:38 +01:00
MerryMage
4ce9c65cfb
reg_alloc: Use std::exchange
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
MerryMage
d124a1d761
emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
...
For CPUs that didn't support SSE4.1, this was a bug.
2020-04-22 20:44:38 +01:00
MerryMage
01a26fa644
fixup: travis: Test with disabled CPU feature detection
2020-04-22 20:44:37 +01:00
MerryMage
30936f5e94
travis: Test with disabled CPU feature detection
...
Ensure that fallbacks are working correctly.
2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30
IR: Add IR instruction VectorZeroUpper
2020-04-22 20:44:37 +01:00
MerryMage
da3e9a5704
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
f698848e26
IR: Add IR instructions A64Memory{Read,Write}128
...
Add the Windows ABI implementation
2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba
IR: Add IR instruction VectorGetElement{8,16,32,64}
2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c
IR: Add IR instruction ZeroExtendToQuad
2020-04-22 20:44:37 +01:00
MerryMage
af848c627d
block_of_code: Add ABI_RETURN2
2020-04-22 20:44:37 +01:00
MerryMage
1749780929
interface: Move Vector typedef to config.h
2020-04-22 20:44:37 +01:00
MerryMage
793753bf63
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c
General: Default constructors and destructors where applicable
2020-04-22 20:44:37 +01:00
MerryMage
db30e02ac8
emit_x64: Extract BlockRangeInformation, remove template parameter
2020-04-22 20:44:36 +01:00
MerryMage
58c4a25527
emit_x64: Use JitStateInfo
2020-04-22 20:42:46 +01:00
MerryMage
eaf545877a
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2020-04-22 20:42:46 +01:00
MerryMage
a554e4a329
backend_x64: Split emit_x64
2020-04-22 20:42:46 +01:00
Lioncash
b612782445
opcodes: Add 64-bit CountLeadingZeroes opcode
2020-04-22 20:42:46 +01:00
Lioncash
b08be71775
a32/a64_emit_x64: Remove unused includes
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
9a812b0c61
reg_alloc: GetBitWidth: Add UNREACHABLE
2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94
IR: Implement Conditional Select
2020-04-22 20:42:45 +01:00
MerryMage
19da68568e
A64/translate/branch: bug: Read-after-write error in BLR
2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5
A64: Implement MOVN, MOVZ, MOVK
2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874
A64: Optimization: Merge interpret blocks
2020-04-22 20:42:45 +01:00
MerryMage
996ffd5488
a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
2020-04-22 20:42:45 +01:00
MerryMage
e4615a4562
emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
72a793f5b0
ir_opt: Split off A32 specific passes
2020-04-22 20:42:45 +01:00
MerryMage
243f06c613
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
10c60dda97
a64_emit_x64: Don't use far code for now
2020-04-22 20:42:45 +01:00
MerryMage
593a569b53
EmitA64SetW: bug: should zero extend to entire 64-bit register
2020-04-22 20:42:45 +01:00
MerryMage
6bd9f02911
EmitA64SetNZCV: bug: to_store is scratch
2020-04-22 20:42:45 +01:00
MerryMage
f0276dd53b
emit_x86: Fix nzcv for EmitSub
2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
e5ace37560
a64_emit_x64: Call interpreter
2020-04-22 20:42:45 +01:00
MerryMage
b12dead76a
A64: Add batch register retrieval to interface
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5
A64: PSTATE access and tests
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7
A64: Implement branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc
A64: Implement pcrel
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
455757d7b6
EmitX64: JitState type as template parameter
2020-04-22 20:39:26 +01:00
MerryMage
2d164d9345
Package up emit context
2020-04-22 20:38:31 +01:00
MerryMage
7bf421dd38
Rename JitState to A32JitState
2020-04-22 20:38:31 +01:00
MerryMage
63bd1ece23
backend_x64: Split A32 specific emission into separate class
2020-04-22 20:38:29 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
dc357c780d
EmitPackedHalvingSub{U,S}16: SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
a98821da41
Merge branch 'misc'
...
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
2020-04-22 20:27:15 +01:00
MerryMage
fc885ac80f
EmitPackedHalvingAddU8: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
4682211729
EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
9ac1c87a51
emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source
2020-04-22 20:27:15 +01:00
MerryMage
6e834de072
Add re-entry prediction to avoid std::unordered_map lookups
2020-04-22 20:26:40 +01:00
MerryMage
984ce22431
emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit
2020-04-22 20:26:40 +01:00
MerryMage
5c6fcf378f
emit_x64: Optimize code emitted by EmitGetCpsr
2020-04-22 20:26:40 +01:00
MerryMage
f595f85039
block_of_code: Remove vzeroupper
2020-04-22 20:26:40 +01:00
MerryMage
4393473d06
interface: Allow saving and storing of contexts
2020-04-22 20:26:40 +01:00
MerryMage
05f3f07704
emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
a3432102b8
jit_state: Split off CPSR.Q
2020-04-22 20:26:40 +01:00
MerryMage
4f8675083c
interface_x64: Fix MSVC cast warning
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
...
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
3cca3bbd0b
jit_state: Split off CPSR.GE
2020-04-22 20:26:40 +01:00
MerryMage
6fde29f5d8
emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory
2020-04-22 20:26:40 +01:00
MerryMage
6adc554b53
jit_state: Hide cpsr implementation
2020-04-22 20:26:40 +01:00
MerryMage
eb80aae9c0
block_of_code: Move MXCSR switching out of dispatch loop
...
Also clarify MXCSR entry/exit terminology
2020-04-22 20:26:40 +01:00
MerryMage
a4e85ad565
emit_x64: Make RSB a stack
2020-04-22 20:26:40 +01:00
MerryMage
2a818f9d8e
Merge branch 'timing'
...
We do this to improve timing information before entering a supervior
function. We also do this to try and stay within JITted code as much
as possible, by updating the cycles we have remaining.
2020-04-22 20:26:37 +01:00
MerryMage
ea4c3292d5
BlockOfCode: Detect space remaining
...
We also clear the code cache when we run out of space.
This closes #111 .
2020-04-22 20:26:12 +01:00
MerryMage
256749910f
Add AddTicks and GetTicksRemaining callbacks
2020-04-22 20:26:12 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
...
Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
639f7cfd2d
reg_alloc: Add IsLastUse optimization for UseScratch
2020-04-22 20:26:12 +01:00
MerryMage
6b122751fe
reg_alloc: Remove reliance on IR::Inst::DecrementRemainingUses
2020-04-22 20:26:12 +01:00
MerryMage
30049ca928
emit_x86: Standardize time of DefineValue call
2020-04-22 20:26:12 +01:00
MerryMage
12eaf496fd
emit_x64: Perform mask creation for packed instructions in SSE
2020-04-22 20:26:07 +01:00
MerryMage
305e4baa29
emit_x64: Eliminate conversion of GE flags
...
* We do this so that we can simplify PackedSelect.
* We also try to minimise xmm-gpr/gpr-xmm transfers in PackedSelect.
2020-04-22 20:26:07 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
18f11972c6
emit_x64: Remove SSSE3 implementation of PackedHalvingAddU8
...
It is much slower than the SSE2 implementation, so there's no point keeping it around.
2020-04-22 20:26:07 +01:00
MerryMage
c4b40909f7
emit_x64: Improve code emission of FPCompare{32,64}
...
Replace if-chain with table lookup
2020-04-22 20:26:07 +01:00
MerryMage
814e378249
VCMP and VCMPE were the other way around
...
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
2020-04-22 20:26:07 +01:00
MerryMage
08f638d447
emit_x64: pmaxuw and pminuw require SSE 4.1
...
This commit is intended to close citra-emu/citra#3137 .
pmaxuw and pminuw were used to perform unsigned comparisons; we emulate
these using a signed comparison by offsetting the inputs by 0x8000 for
CPUs that do not support SSE 4.1.
2020-04-22 20:26:07 +01:00
Mat M
77fe2aeeaa
emit_x64: Amend doxygen parameters for InvalidateCacheRange() ( #116 )
2020-04-22 20:22:01 +01:00
MerryMage
19dcdde90b
block_of_code: Add vzeroupper instructions where AVX-SSE transitions may occur
2020-04-22 20:22:01 +01:00
MerryMage
60d9392b5c
block_of_code: BlockOfCode should provide cpu info
2020-04-22 20:22:01 +01:00
MerryMage
148c01e08f
interface_x64: Remove is_executing assert from HaltExecution
...
In multithreaded code this can be triggered due to a race.
2017-10-14 23:35:01 +01:00
MerryMage
f6cf265bc5
block_of_code: BlockOfCode::ABI_* should be const
2017-09-29 01:35:24 +01:00
MerryMage
29471be317
Standardize location of storage-class specifiers: Place at beginning of declarations
...
Justification: C99 specifies that doing otherwise is an obsolescent feature.
2017-09-29 01:23:45 +01:00
MerryMage
b992e5f8ec
Ranged cache invalidation
...
* Fix clearing code block on a partial invalidation
* Remove unnecessary use of boost::variant
* Code cleanup
2017-09-11 00:11:05 +01:00
MerryMage
568b52d4ba
externals: Update Xbyak to v5.51
...
Xbyak now supports multi-byte nops
2017-08-17 21:34:54 +01:00
MerryMage
1613846ab0
reg_alloc: Handle XMM registers in LoadImmediate
2017-08-16 23:11:05 +01:00
Yuri Kunde Schlesner
38eb7e0314
emit_x64: Use alternative Xbyak names for and, or, xor
...
Also enabled XBYAK_NO_OP_NAMES, allowing us to stop using
-fno-operator-names.
2017-06-12 07:57:46 +01:00
MerryMage
2c9dcfa2db
backend_x64: Rename UnwindHandler to ExceptionHandler
2017-04-20 14:08:56 +01:00
MerryMage
0d47f50f57
block_of_code: Implement farcode
2017-04-19 18:58:36 +01:00
MerryMage
9ac890c62d
reg_alloc: Fix for LLVM's interpretation of the System V ABI
...
This aspect of the System V ABI is under-defined. LLVM choses a
different interpretation from GCC and ICC.
Most other compilers assume the callee is responsible zero-ing the
upper bits of the register if necessary. LLVM assumes the caller
has zero-extended the register.
This is a quick fix for this problem until zext-tracking is
implemented.
2017-04-08 22:12:37 +01:00
MerryMage
a5bb81a97c
backend_x64: Remove dispatch loop in Jit::Run
2017-04-08 10:04:53 +01:00
MerryMage
1b37420459
backend_x64: Simplify dispatcher
2017-04-08 09:35:45 +01:00
MerryMage
4c5de3905b
emit_x64: Correct mutation of immutable in FPThreeOp{32,64}
...
operand (args[1]) was erroneously declared as non-scratch.
operand's value could be modified if FTZ was enabled.
2017-04-01 09:57:14 +01:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
...
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8
Ranged cache invalidation
2017-03-20 11:58:25 +00:00
MerryMage
d9c69ad997
constant_pool: Implement a constant pool
2017-03-19 13:08:04 +00:00
Lioncash
d85137ed65
interface_x64: Amend LLVM disassembly code
...
This would previously attempt to perform pointer arithmetic on void pointers,
which would cause compilation errors.
2017-03-07 18:32:04 +00:00
MerryMage
92a01b0cd8
Prefer ASSERT to DEBUG_ASSERT
2017-02-26 23:30:40 +00:00
MerryMage
135346eb2e
reg_alloc: Move implementations out of header
2017-02-26 23:30:39 +00:00
MerryMage
184db36caf
reg_alloc: Call DecrementRemainingUses in only one place
2017-02-26 23:30:38 +00:00
MerryMage
51fc9fec05
reg_alloc: Reorganize
2017-02-26 23:30:37 +00:00
MerryMage
cf93ab3d31
reg_alloc: Remove old register allocator interface
2017-02-26 23:12:26 +00:00
MerryMage
08a467bf9a
emit_x64: Port to new register allocator interface
2017-02-26 23:12:25 +00:00
MerryMage
f883bad2cc
reg_alloc: New register allocation interface
2017-02-26 21:37:35 +00:00
MerryMage
13ac0c234e
reg_alloc: Differentiate between ReadLock and WriteLock
2017-02-26 21:37:34 +00:00
MerryMage
6c3df057fa
reg_alloc: Remove unused functions
2017-02-26 21:37:33 +00:00
MerryMage
1ee4c07f14
reg_alloc: Reimplement ScratchHostLocReg
2017-02-26 21:37:32 +00:00
MerryMage
640faab8a7
reg_alloc: UseHostLoc is no longer necessary
2017-02-26 21:37:30 +00:00
MerryMage
9518bbe06e
reg_alloc: Reimplement UseScratchHostLocReg
2017-02-26 21:37:29 +00:00
MerryMage
e1d8238c50
reg_alloc: Stub UseOpArg
2017-02-26 21:37:27 +00:00
MerryMage
2b078152e7
reg_alloc: Reimplement UseHostLocReg
2017-02-26 21:37:26 +00:00
MerryMage
aefe550428
reg_alloc: Remove the Def concept from register allocator internals
2017-02-26 21:37:25 +00:00
MerryMage
65cccf070e
reg_alloc: Properly encapsulate HostLocInfo
2017-02-26 21:37:24 +00:00
MerryMage
469bb6253f
backend_x64: Factor EmitExclusiveWriteMemory64 into ExclusiveWrite
2017-02-26 15:34:26 +00:00
MerryMage
d7ab1f9c64
backend_x64: Fix ABI violation in ReadMemory and WriteMemory
...
Caller-save registers were not saved before call instruction.
Refer to issue #98 .
2017-02-26 15:34:25 +00:00
MerryMage
3768174783
ir_opt: Constant propagation pass works better with a DCE just before it
2017-02-26 15:28:35 +00:00
MerryMage
bbeea72eba
ir_opt: Remove redundant shift instructions
2017-02-26 15:28:14 +00:00
MerryMage
517fe0f18e
emit_x64: WriteMemory* microinstructions do not define a value
2017-02-25 11:54:47 +00:00
MerryMage
1ff60bc69f
reg_alloc: Move OpArg into own header
2017-02-21 23:38:36 +00:00
MerryMage
058f7b5de6
emit_x64: Make EmitTerminal type-safe
...
Avoid the use of boost::variant::which, which tends to produce code which
is not verifiable at compile-time.
2017-02-16 19:40:51 +00:00
MerryMage
2af39dfaa8
emit_x64: Make reg_alloc a local variable
...
reg_alloc contains state that is only valid on a per-block basis, so there
is no reason for it to be a member variable.
2017-02-04 09:29:35 +00:00
MerryMage
a0e9417912
ir_opt: Initial constant propagation pass implementation
2017-01-30 21:49:46 +00:00
MerryMage
2447f2f360
callbacks: Factorize memory callbacks into inner structure
2017-01-30 21:42:51 +00:00
MerryMage
9ecdd32b84
coprocessor: Implement fast-path for Coproc{Send,Get}{OneWord,TwoWords}
...
Allow coprocessor interface to provide pointers instead of a callback.
This allows for a fastpath when all that is required is to read or write a
value and no other action needs to be taken.
2017-01-08 14:56:06 +00:00
MerryMage
48693eb6ff
Implement coprocessor-related microinstructions
...
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c
Implement UHASX, UHSAX, SHASX and SHSAX ( #75 )
2016-12-28 21:32:22 +00:00
MerryMage
c7e5216473
emit_x64: EraseInstruction now also invalidates the instruction
...
There is now no longer a need to call DecrementRemainingUses on the parent
instruction.
2016-12-22 18:43:11 +00:00
Fernando Sahmkow
677f62dd6f
Implement SHSUB8 and SHSUB16 ( #74 )
...
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
MerryMage
36082087de
callbacks: Read code using MemoryReadCode callback
2016-12-21 21:39:14 +00:00
MerryMage
6a269a6ebd
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 19:51:25 +00:00
MerryMage
02b2ab7581
emit_x64: Pass tmp to ExtractMostSignificantBitFromPackedBytes in EmitPackedAddU8
2016-12-20 22:07:51 +00:00
MerryMage
097f6a83da
emit_x64: Document ExtractAndDuplicateMostSignificantBitFromPackedWords
2016-12-20 22:06:14 +00:00
MerryMage
03f168094d
emit_x64: Document ExtractMostSignificantBitFromPackedBytes
2016-12-20 22:05:51 +00:00
FernandoS27
8919265d2c
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245
Implemented USAD8 and USADA8
2016-12-20 21:52:38 +00:00
MerryMage
b1d3e7aae9
emit_x64: Refactor patching code
...
* Only have a single std::unordered_map for patching information
* Factor patch emitters into own functions
* Implement EmitX64::Unpatch
2016-12-20 14:06:55 +00:00
MerryMage
74a95ea51e
block_of_code: Rename alloc to AllocateFromCodeSpace
2016-12-18 23:43:48 +00:00
MerryMage
96e46ba6b5
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:34:29 +00:00
MerryMage
276873bf70
Wrap #pragma warning with #ifdef _MSC_VER .. #endif
2016-12-15 21:36:02 +00:00
MerryMage
0e8b626d87
CMakeLists: Globally disable MSVC warning C4592
...
C4592: Symbol will be dynamically initialized (implementation limitation)
2016-12-15 21:09:55 +00:00
MerryMage
91e851a991
CMakeLists: Enable /W4 on MSVC
2016-12-15 20:52:23 +00:00
MerryMage
63caed7b09
emit_x64: Remove argument names of unused arguments
2016-12-15 20:52:22 +00:00
MerryMage
5bea2e1680
block_of_code: Support stack unwinding on Windows
2016-12-12 07:49:18 +00:00
MerryMage
4962d92b79
block_of_code: Do not regenerate prelude when clearing cache
2016-12-12 07:49:18 +00:00