MerryMage
db30e02ac8
emit_x64: Extract BlockRangeInformation, remove template parameter
2020-04-22 20:44:36 +01:00
MerryMage
58c4a25527
emit_x64: Use JitStateInfo
2020-04-22 20:42:46 +01:00
MerryMage
a554e4a329
backend_x64: Split emit_x64
2020-04-22 20:42:46 +01:00
Lioncash
b612782445
opcodes: Add 64-bit CountLeadingZeroes opcode
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94
IR: Implement Conditional Select
2020-04-22 20:42:45 +01:00
MerryMage
e4615a4562
emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
f0276dd53b
emit_x86: Fix nzcv for EmitSub
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
455757d7b6
EmitX64: JitState type as template parameter
2020-04-22 20:39:26 +01:00
MerryMage
2d164d9345
Package up emit context
2020-04-22 20:38:31 +01:00
MerryMage
7bf421dd38
Rename JitState to A32JitState
2020-04-22 20:38:31 +01:00
MerryMage
63bd1ece23
backend_x64: Split A32 specific emission into separate class
2020-04-22 20:38:29 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
dc357c780d
EmitPackedHalvingSub{U,S}16: SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
a98821da41
Merge branch 'misc'
...
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
2020-04-22 20:27:15 +01:00
MerryMage
fc885ac80f
EmitPackedHalvingAddU8: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
4682211729
EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
9ac1c87a51
emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source
2020-04-22 20:27:15 +01:00
MerryMage
984ce22431
emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit
2020-04-22 20:26:40 +01:00
MerryMage
5c6fcf378f
emit_x64: Optimize code emitted by EmitGetCpsr
2020-04-22 20:26:40 +01:00
MerryMage
05f3f07704
emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
a3432102b8
jit_state: Split off CPSR.Q
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
...
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
3cca3bbd0b
jit_state: Split off CPSR.GE
2020-04-22 20:26:40 +01:00
MerryMage
6fde29f5d8
emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory
2020-04-22 20:26:40 +01:00
MerryMage
6adc554b53
jit_state: Hide cpsr implementation
2020-04-22 20:26:40 +01:00
MerryMage
eb80aae9c0
block_of_code: Move MXCSR switching out of dispatch loop
...
Also clarify MXCSR entry/exit terminology
2020-04-22 20:26:40 +01:00
MerryMage
a4e85ad565
emit_x64: Make RSB a stack
2020-04-22 20:26:40 +01:00
MerryMage
256749910f
Add AddTicks and GetTicksRemaining callbacks
2020-04-22 20:26:12 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
...
Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
30049ca928
emit_x86: Standardize time of DefineValue call
2020-04-22 20:26:12 +01:00
MerryMage
12eaf496fd
emit_x64: Perform mask creation for packed instructions in SSE
2020-04-22 20:26:07 +01:00
MerryMage
305e4baa29
emit_x64: Eliminate conversion of GE flags
...
* We do this so that we can simplify PackedSelect.
* We also try to minimise xmm-gpr/gpr-xmm transfers in PackedSelect.
2020-04-22 20:26:07 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
18f11972c6
emit_x64: Remove SSSE3 implementation of PackedHalvingAddU8
...
It is much slower than the SSE2 implementation, so there's no point keeping it around.
2020-04-22 20:26:07 +01:00
MerryMage
c4b40909f7
emit_x64: Improve code emission of FPCompare{32,64}
...
Replace if-chain with table lookup
2020-04-22 20:26:07 +01:00