Tillmann Karras
dad7724b86
TranlateArm: implement remaining multiplies
...
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
2016-08-19 01:08:38 +01:00
MerryMage
fe15cbd50e
translate_arm/parallel: Detect UNPREDICTABLE instructions
2016-08-19 00:59:07 +01:00
MerryMage
2119dfc926
translate_arm/multiply: MLA is UNPREDICTABLE when Ra == R15
2016-08-19 00:59:05 +01:00
MerryMage
0d0f4b1b4f
translate_arm/load_store: Correct implementation for LDM*
2016-08-19 00:59:04 +01:00
MerryMage
4acc481463
translate_arm/load_store: Handle unpredictable instructions
...
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:
a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors
I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
2016-08-19 00:59:02 +01:00
MerryMage
b8cf43c43e
translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions
2016-08-18 18:23:05 +01:00
MerryMage
7d7ac0af71
Optimization: Make SVC use RSB
2016-08-15 15:02:08 +01:00
MerryMage
e164ede4dc
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
2016-08-15 11:50:49 +01:00
bunnei
30f3d869cc
TranslateArm: Implement VPUSH and VPOP.
2016-08-13 19:37:03 +01:00
MerryMage
960d14d18e
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb
TranslateArm: Implement QSUB8.
2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2
TranslateArm: Implement UQSUB8.
2016-08-12 19:00:44 +01:00
MerryMage
3808938c98
Fix SETEND
2016-08-11 19:15:58 +01:00
bunnei
218980cf69
load_store: Implement LDRSB and LDRSH.
2016-08-11 17:18:20 +01:00
MerryMage
0e5593ba62
TranslateArm: Implement SETEND
2016-08-11 17:15:33 +01:00
MerryMage
b4c586d5ef
TranslateArm: VSTR: Correct behaviour in big-endian mode
2016-08-10 16:43:37 +01:00
bunnei
8e8db6e137
TranslateArm: Implement VSTR.
2016-08-10 15:01:23 +01:00
MerryMage
df39308e03
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:57:20 +01:00
MerryMage
d0d51ba346
TranslateArm: Implement STM, STMDA, STMDB, STMIB
2016-08-08 22:49:11 +01:00
MerryMage
85549d7ae2
TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
2016-08-08 22:26:06 +01:00
MerryMage
edb236ab07
Correct implementation of thumb16_SVC and arm_SVC
2016-08-07 22:19:39 +01:00
MerryMage
4dcd1d1859
Arm: BLX is UNPREDICTABLE when Rm is PC
2016-08-07 20:50:33 +01:00
MerryMage
1af5bef32c
TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
2016-08-07 20:40:31 +01:00
MerryMage
939bb5c0cb
TranslateArm: Implement NOP
2016-08-07 20:08:31 +01:00
MerryMage
e48df9d8fd
TranslateArm: Implement Hint instructions as NOPs
2016-08-07 20:04:48 +01:00
MerryMage
3a465ba4a8
VFP: Implement VLDR
2016-08-07 19:59:35 +01:00
MerryMage
a2c2db277b
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
MerryMage
0f412247ed
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
MerryMage
cd8e7c0504
VFP: Implement VNEG
2016-08-07 12:04:21 +01:00
MerryMage
da33af5abe
VFP: Implement VMLA, VMLS, VNMLA, VNMLS
2016-08-07 11:49:06 +01:00
MerryMage
3f1345a1a5
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f
VFP: Implement VSUB
2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
MerryMage
c35f06470f
VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
2016-08-06 23:01:18 +01:00
Tillmann Karras
55204a80d0
Implement SMMLA, SMMLS, SMMUL
2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f
Add carry support to MostSignificantWord
2016-08-06 21:17:11 +01:00
MerryMage
7915f97d98
TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
2016-08-06 20:42:06 +01:00
MerryMage
4b31ea25a7
VFP: Implement VADD.{F32,F64}
2016-08-06 20:03:15 +01:00
MerryMage
8ff414ee0e
Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
2016-08-06 20:03:15 +01:00
bunnei
2448d52394
load_store: Use correct types for LDR/STR.
2016-08-05 20:51:32 -04:00
bunnei
8c2300d477
arm: Implement LDRD reg/imm instructions.
2016-08-05 20:05:02 -04:00
bunnei
ec3a98cf95
arm: Implement LDRH reg/imm instructions.
2016-08-05 20:05:01 -04:00
bunnei
192a0fba7a
arm: Implement LDRB reg/imm instructions.
2016-08-05 20:05:00 -04:00
bunnei
dfb318f208
arm: Implement STRD reg/imm instructions.
2016-08-05 20:04:59 -04:00
bunnei
e931dc2496
arm: Implement STRH reg/imm instructions.
2016-08-05 20:04:58 -04:00
bunnei
9f77662b24
arm: Implement STRB reg/imm instructions.
2016-08-05 20:04:57 -04:00
bunnei
caab1bbc7c
arm: Implement STR reg/imm instructions.
2016-08-05 20:04:56 -04:00
