MerryMage
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cb481a3a48
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A64: Implement compare and branch
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
23f3afe0b3
|
A64: Implement branch (register)
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
0641445e51
|
A64: Implement logical
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
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c09e69bb97
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A64: Implement addsub instructions
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2020-04-22 20:42:44 +01:00 |
|
MerryMage
|
d1cef6ffb0
|
A64: Implement ADD_shifted
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2020-04-22 20:42:44 +01:00 |
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MerryMage
|
44f7f04b5c
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IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
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2020-04-22 20:39:27 +01:00 |
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MerryMage
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8bef20c24d
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IR: Split off A32 specific opcodes
|
2020-04-22 20:33:32 +01:00 |
|
MerryMage
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19a7fb8992
|
jit_state: Split off CPSR.NZCV
|
2020-04-22 20:26:40 +01:00 |
|
MerryMage
|
d1e0a29cd9
|
Implement IR instruction PackedSelect, reimplement SEL
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2020-04-22 20:26:07 +01:00 |
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MerryMage
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05e97058c3
|
parallel: Add and Subtract with Exchange improvements
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
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2017-03-24 15:56:24 +00:00 |
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MerryMage
|
bbeea72eba
|
ir_opt: Remove redundant shift instructions
|
2017-02-26 15:28:14 +00:00 |
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MerryMage
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48693eb6ff
|
Implement coprocessor-related microinstructions
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
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2017-01-08 14:56:06 +00:00 |
|
MerryMage
|
1efd3a764d
|
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
|
2017-01-05 20:16:39 +00:00 |
|
FernandoS27
|
d5610eb26c
|
Implement UHASX, UHSAX, SHASX and SHSAX (#75)
|
2016-12-28 21:32:22 +00:00 |
|
Fernando Sahmkow
|
677f62dd6f
|
Implement SHSUB8 and SHSUB16 (#74)
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
|
2016-12-22 12:02:24 +00:00 |
|
MerryMage
|
6a269a6ebd
|
IR: Add microinstructions UnsignedSaturation and SignedSaturation
|
2016-12-21 19:51:25 +00:00 |
|
FernandoS27
|
8919265d2c
|
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
|
2016-12-20 21:52:38 +00:00 |
|
FernandoS27
|
3f6ecfe245
|
Implemented USAD8 and USADA8
|
2016-12-20 21:52:38 +00:00 |
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MerryMage
|
96e46ba6b5
|
Implement QADD, QSUB, QDADD, QDSUB
|
2016-12-15 22:34:29 +00:00 |
|
MerryMage
|
52e1445f43
|
Implement USUB8
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2016-12-05 00:29:15 +00:00 |
|
MerryMage
|
5c1aab1666
|
Implement CLZ
Includes tests
|
2016-12-04 22:56:33 +00:00 |
|
MerryMage
|
1a1646d962
|
Implement UADD8
|
2016-12-04 20:52:33 +00:00 |
|
MerryMage
|
7cad6949e7
|
IR: Implement new pseudo-operation GetGEFromOp
|
2016-12-04 20:52:06 +00:00 |
|
MerryMage
|
e166965f3e
|
Implement VCMP
|
2016-12-03 11:41:09 +00:00 |
|
Merry
|
0ff8c375af
|
Implement UHSUB8 and UHSUB16 (#48)
|
2016-11-26 18:27:21 +00:00 |
|
Merry
|
cb17f9a3ed
|
Implement SHADD8 and SHADD16 (#47)
|
2016-11-26 18:12:29 +00:00 |
|
MerryMage
|
c0c1bb1094
|
Implemented UHADD16
|
2016-11-26 11:28:20 +00:00 |
|
Sebastian Valle
|
4d44474ad4
|
Implemented the ARM UHADD8 instruction. (#45)
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
|
2016-11-25 20:32:22 +00:00 |
|
MerryMage
|
b6f7b8babd
|
ir: Implement GetGEFlags, SetGEFlags
|
2016-11-23 19:44:27 +00:00 |
|
MerryMage
|
dca3b2f079
|
Implement VMRS and VMSR
|
2016-08-26 22:47:54 +01:00 |
|
MerryMage
|
b5a86889cd
|
Implement VCVT
|
2016-08-23 22:20:04 +01:00 |
|
MerryMage
|
e164ede4dc
|
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
|
2016-08-15 11:50:49 +01:00 |
|
MerryMage
|
960d14d18e
|
Optimization: Implement Return Stack Buffer
|
2016-08-13 00:10:23 +01:00 |
|
bunnei
|
8e68e6fdd9
|
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
|
2016-08-12 19:00:44 +01:00 |
|
bunnei
|
4b09c0d032
|
TranslateArm: Implement QADD8 and UQADD8.
|
2016-08-12 19:00:44 +01:00 |
|
bunnei
|
127fbe99cb
|
TranslateArm: Implement QSUB8.
|
2016-08-12 19:00:44 +01:00 |
|
bunnei
|
86fe29c6d2
|
TranslateArm: Implement UQSUB8.
|
2016-08-12 19:00:44 +01:00 |
|
MerryMage
|
df39308e03
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
|
2016-08-09 22:57:20 +01:00 |
|
Tillmann Karras
|
5d26899ac9
|
Add simplified LogicalShiftRight64 IR opcode
|
2016-08-08 22:27:05 +01:00 |
|
Tillmann Karras
|
ccb2aa96a5
|
Add support for the APSR.Q flag
|
2016-08-08 22:27:04 +01:00 |
|
MerryMage
|
a2c2db277b
|
VFP: Implement VMOV (all variants)
|
2016-08-07 19:25:12 +01:00 |
|
MerryMage
|
0f412247ed
|
VFP: Implement VSQRT
|
2016-08-07 12:19:07 +01:00 |
|
MerryMage
|
3f1345a1a5
|
VFP: Implement VNMUL, VDIV
|
2016-08-07 10:56:12 +01:00 |
|
MerryMage
|
12e7f2c359
|
VFP: Implement VMUL
|
2016-08-07 10:21:14 +01:00 |
|
MerryMage
|
97b5fa173f
|
VFP: Implement VSUB
|
2016-08-07 01:45:52 +01:00 |
|
MerryMage
|
ce6b5f8210
|
VFP: Implement VABS
|
2016-08-07 01:27:18 +01:00 |
|
Tillmann Karras
|
846d07d7b5
|
Add Sub64 opcode
|
2016-08-06 21:17:11 +01:00 |
|
MerryMage
|
4b31ea25a7
|
VFP: Implement VADD.{F32,F64}
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
640ce48baa
|
VFP: Implement {Get,Set}ExtendedRegister{32,64}
|
2016-08-05 19:06:10 +01:00 |
|
MerryMage
|
b4aa01ccf4
|
Merge remote-tracking branch 'tilkax/master'
|
2016-08-05 14:14:06 +01:00 |
|